From 12bb7973ef6832897ebf57949fd3bf89ad60862e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 6 Oct 2019 13:59:12 +0100 Subject: [PATCH] Fixes for Tegra Jetson TX1/TX2 series via max77620 --- ...-Use-correct-unit-for-debounce-times.patch | 586 ++++++++++++++++++ kernel.spec | 7 + ...ax77620-Do-not-allocate-IRQs-upfront.patch | 183 ++++++ 3 files changed, 776 insertions(+) create mode 100644 gpio-max77620-Use-correct-unit-for-debounce-times.patch create mode 100644 mfd-max77620-Do-not-allocate-IRQs-upfront.patch diff --git a/gpio-max77620-Use-correct-unit-for-debounce-times.patch b/gpio-max77620-Use-correct-unit-for-debounce-times.patch new file mode 100644 index 000000000..bcf575fb8 --- /dev/null +++ b/gpio-max77620-Use-correct-unit-for-debounce-times.patch @@ -0,0 +1,586 @@ +From patchwork Wed Oct 2 12:28:23 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1170631 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=none (mailfrom) smtp.mailfrom=vger.kernel.org + (client-ip=209.132.180.67; helo=vger.kernel.org; + envelope-from=linux-gpio-owner@vger.kernel.org; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=gmail.com +Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; + unprotected) header.d=gmail.com header.i=@gmail.com + header.b="Xe4ozWCs"; dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by ozlabs.org (Postfix) with ESMTP id 46jwR31mYjz9sPl + for ; + Wed, 2 Oct 2019 22:28:31 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1725875AbfJBM2a (ORCPT ); + Wed, 2 Oct 2019 08:28:30 -0400 +Received: from mail-wr1-f67.google.com ([209.85.221.67]:42402 "EHLO + mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1725848AbfJBM23 (ORCPT + ); Wed, 2 Oct 2019 08:28:29 -0400 +Received: by mail-wr1-f67.google.com with SMTP id n14so19415351wrw.9; + Wed, 02 Oct 2019 05:28:28 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=qP9mbplmTy0EguziRYmdZKFvmKZpgiY1goXlhQxV0/8=; + b=Xe4ozWCsxpb6DK1agUyM9eUxlP6G03BBFhI5g4JErak3F1hsMTKXmoyANoMKXxS+UF + OWRiAkrVC3cQOJczX/+7HhZQ8bMC3apl96os1jO6/JWJEP2BHZpDAF0bRyJQdbd0lmMA + afH1TDc/aCLYhrc6UF4IMSf4Noe9cSvoyQYpo0qgpxktdn7I/jv5ztIFWEVBOuEfDveP + hKAmMRuOGlokBd9/+TirOM307HbJYDWAZ8Wko3G+bYcw41RSULf9eN0mQPLmeF/+J9tC + XwaypBneeu3VeCmfU/DxP1duZ3pCcnwOu5nrzdHsS6ow28T2CVk8VvAAZGEU1cUIX4Z+ + +hkw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=qP9mbplmTy0EguziRYmdZKFvmKZpgiY1goXlhQxV0/8=; + b=akVGfKDGN9KlaS7GfDnHx98C2QeedcAeu8RIoCS8uh0twWVOZMZKbUY6M/2HaZKsPI + 38mOkZ2CRPyO1EzbpI9UU6hHXfohMTHuWX0pTdvkFXn+TfZPAxJa1fVRhHgOcknkhb/U + JBzse/qoFFdlsRK3kY6I+0R1YyyAD2SDlzfax4U6ew8DL0icpWegiNEXnIno/7b6sIt2 + 9u9PEHk+1AdQkgS/tVRAFdVg6rrYMbUFkh1JAYsEED71D2IR38JmdUfjsW0Bi1aohXuz + F8LOoB0G33BszHljgknOYlHF4tPGDitMVI+giV3UgwXEWHKFgimUJKOb1nyg+4fcVOLO + 2g1g== +X-Gm-Message-State: APjAAAX5YpK/Xf8BgNQ7EyD7TzARRLtN4fRfLcEXIT3fZkDHf5xGyxPi + jnbTBpi+UDekDgGOQiVnsoo= +X-Google-Smtp-Source: APXvYqw9HA6mSwE4O/MajE0OyTuT/xQaPqMRcrU+p/RXgMiP+Q297cH5ORneUFjHbOQpwrdgestsJw== +X-Received: by 2002:adf:fe05:: with SMTP id n5mr2716992wrr.355.1570019307315; + Wed, 02 Oct 2019 05:28:27 -0700 (PDT) +Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) + by smtp.gmail.com with ESMTPSA id + e17sm5719759wma.15.2019.10.02.05.28.25 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 02 Oct 2019 05:28:26 -0700 (PDT) +From: Thierry Reding +To: Linus Walleij , + Bartosz Golaszewski +Cc: Timo Alho , linux-gpio@vger.kernel.org, + linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org +Subject: [PATCH 1/3] gpio: max77620: Use correct unit for debounce times +Date: Wed, 2 Oct 2019 14:28:23 +0200 +Message-Id: <20191002122825.3948322-1-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.23.0 +MIME-Version: 1.0 +Sender: linux-gpio-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-gpio@vger.kernel.org + +From: Thierry Reding + +The gpiod_set_debounce() function takes the debounce time in +microseconds. Adjust the switch/case values in the MAX77620 GPIO to use +the correct unit. + +Signed-off-by: Thierry Reding +--- + drivers/gpio/gpio-max77620.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c +index 47d05e357e61..faf86ea9c51a 100644 +--- a/drivers/gpio/gpio-max77620.c ++++ b/drivers/gpio/gpio-max77620.c +@@ -192,13 +192,13 @@ static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio, + case 0: + val = MAX77620_CNFG_GPIO_DBNC_None; + break; +- case 1 ... 8: ++ case 1000 ... 8000: + val = MAX77620_CNFG_GPIO_DBNC_8ms; + break; +- case 9 ... 16: ++ case 9000 ... 16000: + val = MAX77620_CNFG_GPIO_DBNC_16ms; + break; +- case 17 ... 32: ++ case 17000 ... 32000: + val = MAX77620_CNFG_GPIO_DBNC_32ms; + break; + default: + +From patchwork Wed Oct 2 12:28:24 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1170635 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=none (mailfrom) smtp.mailfrom=vger.kernel.org + (client-ip=209.132.180.67; helo=vger.kernel.org; + envelope-from=linux-gpio-owner@vger.kernel.org; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=gmail.com +Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; + unprotected) header.d=gmail.com header.i=@gmail.com + header.b="ZNLKx8UP"; dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by ozlabs.org (Postfix) with ESMTP id 46jwRG4D1Dz9sPj + for ; + Wed, 2 Oct 2019 22:28:42 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726684AbfJBM2d (ORCPT ); + Wed, 2 Oct 2019 08:28:33 -0400 +Received: from mail-wr1-f66.google.com ([209.85.221.66]:43919 "EHLO + mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1725848AbfJBM2c (ORCPT + ); Wed, 2 Oct 2019 08:28:32 -0400 +Received: by mail-wr1-f66.google.com with SMTP id q17so19436519wrx.10; + Wed, 02 Oct 2019 05:28:30 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=iB2sFoZ4x2KF5IYNHgeqY98wXl2bB2JULeTFtyoqdVY=; + b=ZNLKx8UP+ukUsboEbPQ9oqLgg5M+37mex1mpr0SgaI7zjToRbmdCJL/chPAEK2r7t8 + C+RcBU7oQnbO3L1hTZQh1VyMX84xXmn0x8g7AskW0bydPo29O2lwBgM9BeNJiMt7gaS7 + LtCbNGe/ttaTfoTsJSOmpLgAJLVJ7mpN5r3h18HtAYcsB5NqjcgFF1yFZ9FvmXOIhxAm + 1MxDJ7tO9pJbc4JQ8iR/yPEsCNibvlX1qtkuBUWdy6aJHG4CkqIbqb+V+84d3R5bsmoe + sDx7f/mMbJ6cF7dCarqOe47Quscz7UkGw/gZywhaYNS/7p6JBvKDCe0bbruzj3MEXMRy + 2tlw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=iB2sFoZ4x2KF5IYNHgeqY98wXl2bB2JULeTFtyoqdVY=; + b=E8tcBQ6lyFYE0z3JyOT1cT/Bgc194gfYXxSrFLZnHENJjrNz2Ijr9mgmTvanMcmLgs + qvPIH6L5rKKzPpmhxkGCVNMunQuR3U4+g4lCHaJuDE3QikN/dAMpfidmgej7UBcnxYXq + c8yhdhWsg36bVdUYmTdrPVNYayH3WqNj6h3724+nRQnwGs5Y+emoWuhckIBZQR2fJd3Z + jEEmej1F2QBBv4/Cf7RoOd9BVX1DFI3LgOoGADQcGnuCW/+2clFWp860wnWLGdTGqPKI + KCaPoNOzFDkbQCyhebPt8recsiTexB8AmRdTCOszf/TYQwmlvVUUSVqdwY4/P2N0uAGO + 8kOA== +X-Gm-Message-State: APjAAAVWUbix6mCYosiAjDRWTB69Pz3baQGdU6UKJJJba2d6nCyRFzs3 + w1iyx5KVIbR84BwLezjxgUk= +X-Google-Smtp-Source: APXvYqylRlhdhO5L5gTZTUh+KEGBPZYsf15BqzctBqRpCy2v75DzIQkOOs8h+NZd8ePk6530OH8SlA== +X-Received: by 2002:adf:f112:: with SMTP id r18mr2493221wro.88.1570019309276; + Wed, 02 Oct 2019 05:28:29 -0700 (PDT) +Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) + by smtp.gmail.com with ESMTPSA id + h17sm10777194wme.6.2019.10.02.05.28.28 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 02 Oct 2019 05:28:28 -0700 (PDT) +From: Thierry Reding +To: Linus Walleij , + Bartosz Golaszewski +Cc: Timo Alho , linux-gpio@vger.kernel.org, + linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org +Subject: [PATCH 2/3] gpio: max77620: Do not allocate IRQs upfront +Date: Wed, 2 Oct 2019 14:28:24 +0200 +Message-Id: <20191002122825.3948322-2-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.23.0 +In-Reply-To: <20191002122825.3948322-1-thierry.reding@gmail.com> +References: <20191002122825.3948322-1-thierry.reding@gmail.com> +MIME-Version: 1.0 +Sender: linux-gpio-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-gpio@vger.kernel.org + +From: Thierry Reding + +regmap_add_irq_chip() will try to allocate all of the IRQ descriptors +upfront if passed a non-zero irq_base parameter. However, the intention +is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0 +instead of -1 to fix that use-case. + +Signed-off-by: Thierry Reding +--- + drivers/gpio/gpio-max77620.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c +index faf86ea9c51a..c58b56e5291e 100644 +--- a/drivers/gpio/gpio-max77620.c ++++ b/drivers/gpio/gpio-max77620.c +@@ -304,7 +304,7 @@ static int max77620_gpio_probe(struct platform_device *pdev) + } + + ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, gpio_irq, +- IRQF_ONESHOT, -1, ++ IRQF_ONESHOT, 0, + &max77620_gpio_irq_chip, + &chip->gpio_irq_data); + if (ret < 0) { + +From patchwork Wed Oct 2 12:28:25 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1170633 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=none (mailfrom) smtp.mailfrom=vger.kernel.org + (client-ip=209.132.180.67; helo=vger.kernel.org; + envelope-from=linux-gpio-owner@vger.kernel.org; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=gmail.com +Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; + unprotected) header.d=gmail.com header.i=@gmail.com + header.b="TsA9TpB7"; dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by ozlabs.org (Postfix) with ESMTP id 46jwRD5mmDz9sPq + for ; + Wed, 2 Oct 2019 22:28:40 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1727456AbfJBM2f (ORCPT ); + Wed, 2 Oct 2019 08:28:35 -0400 +Received: from mail-wm1-f66.google.com ([209.85.128.66]:34525 "EHLO + mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1726682AbfJBM2e (ORCPT + ); Wed, 2 Oct 2019 08:28:34 -0400 +Received: by mail-wm1-f66.google.com with SMTP id y135so4823030wmc.1; + Wed, 02 Oct 2019 05:28:32 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=CBafHZOcPLRsPg6HMh6RW3fmvKDiW2MODjit57xEepE=; + b=TsA9TpB72Q02EPmaBqcc4zzucsjsdc5mtjgAgTak5YrKh+mRT2HMioWeCxrLu5Cl+6 + 66PhcUzrRtOnct3yEqC1hueFX+K8TsDr1bJq2f3L5LqA9rYz5Hdk93jVmwyEKtrPUOa5 + DNgu/r4ppuWX/d9nuLpVLcFGOzWYjz/GSfyRm/B0MNSsiIFx/VfjsK6OQk48uN2gyMPf + LsirANA0HYZPyXaUFBkchtTE71HqGFSIzJGUSVGm12Z26puMZ9GiUid1l1XJjdDuFfhU + 3k9TQnvLEpZDHArb2G8JrwRI8fRZ/OBDLPyKvH/EEdDYa/FfJOzliZBqMgVFpXpXGTZ6 + 7YAw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=CBafHZOcPLRsPg6HMh6RW3fmvKDiW2MODjit57xEepE=; + b=MVU3M5NDj2W8TitA2MM98hE9Vgb07UODtrRolwf9TaeTgf2XRMgYAWr9v5zaHvBU2q + 4q/HPqbn0WAW3OBfSQLW6CFcdiHOkjfR+r8tKHpNMNBbeDrj1DeeKE/A25plLXxg+Ypz + 1bKJe6DPvjIqLvrpVmPADaRtsAkgDFTt/h41ti2uTwS5xq4qEf1mwz6lFyJkGyf+Qjb5 + pnViJ3Lv89RLBvJwWj0j2t/EzzznPZn9xP663YkNrUNRYrAM7ZBauvK7kMyf8LnKo96E + +niJu7OV4PnRspOC8AS3PPM4DHGctXZl6QMcJ1LyPwBkd8EHJioV1iDJKqHQIbxew46f + AzCA== +X-Gm-Message-State: APjAAAWbRYKoHNSgs+vkRdoNeam2jbbuVKAFxN3ysahEdBul5DIjNFsz + JRjkPkilW+LPTwy2EmDLNUE= +X-Google-Smtp-Source: APXvYqyfSTFvcH9+iLVzVGJ5KDEauN0ssdr9eBfIIdRWe8prWnP7KBGuKItc0GAk8lMLMDzdLKlWtw== +X-Received: by 2002:a1c:7306:: with SMTP id d6mr2864027wmb.62.1570019311374; + Wed, 02 Oct 2019 05:28:31 -0700 (PDT) +Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) + by smtp.gmail.com with ESMTPSA id + 90sm3179450wrr.1.2019.10.02.05.28.30 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 02 Oct 2019 05:28:30 -0700 (PDT) +From: Thierry Reding +To: Linus Walleij , + Bartosz Golaszewski +Cc: Timo Alho , linux-gpio@vger.kernel.org, + linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org +Subject: [PATCH 3/3] gpio: max77620: Fix interrupt handling +Date: Wed, 2 Oct 2019 14:28:25 +0200 +Message-Id: <20191002122825.3948322-3-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.23.0 +In-Reply-To: <20191002122825.3948322-1-thierry.reding@gmail.com> +References: <20191002122825.3948322-1-thierry.reding@gmail.com> +MIME-Version: 1.0 +Sender: linux-gpio-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-gpio@vger.kernel.org + +From: Timo Alho + +The interrupt-related register fields on the MAX77620 GPIO controller +share registers with GPIO related fields. If the IRQ chip is implemented +with regmap-irq, this causes the IRQ controller code to overwrite fields +previously configured by the GPIO controller code. + +Two examples where this causes problems are the NVIDIA Jetson TX1 and +Jetson TX2 boards, where some of the GPIOs are used to enable vital +power regulators. The MAX77620 GPIO controller also provides the USB OTG +ID pin. If configured as an interrupt, this causes some of the +regulators to be powered off. + +Signed-off-by: Timo Alho +Signed-off-by: Thierry Reding +--- + drivers/gpio/gpio-max77620.c | 231 ++++++++++++++++++----------------- + 1 file changed, 117 insertions(+), 114 deletions(-) + +diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c +index c58b56e5291e..c5b64a4ac172 100644 +--- a/drivers/gpio/gpio-max77620.c ++++ b/drivers/gpio/gpio-max77620.c +@@ -18,109 +18,115 @@ struct max77620_gpio { + struct gpio_chip gpio_chip; + struct regmap *rmap; + struct device *dev; ++ struct mutex buslock; /* irq_bus_lock */ ++ unsigned int irq_type[8]; ++ bool irq_enabled[8]; + }; + +-static const struct regmap_irq max77620_gpio_irqs[] = { +- [0] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 0, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [1] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 1, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [2] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 2, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [3] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 3, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [4] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 4, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [5] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 5, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [6] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 6, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +- [7] = { +- .reg_offset = 0, +- .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, +- .type = { +- .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, +- .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, +- .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, +- .type_reg_offset = 7, +- .types_supported = IRQ_TYPE_EDGE_BOTH, +- }, +- }, +-}; ++static irqreturn_t max77620_gpio_irqhandler(int irq, void *data) ++{ ++ struct max77620_gpio *gpio = data; ++ unsigned int value, offset; ++ unsigned long pending; ++ int err; ++ ++ err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value); ++ if (err < 0) { ++ dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err); ++ return IRQ_NONE; ++ } ++ ++ pending = value; ++ ++ for_each_set_bit(offset, &pending, 8) { ++ unsigned int virq; ++ ++ virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset); ++ handle_nested_irq(virq); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void max77620_gpio_irq_mask(struct irq_data *data) ++{ ++ struct gpio_chip *chip = irq_data_get_irq_chip_data(data); ++ struct max77620_gpio *gpio = gpiochip_get_data(chip); ++ ++ gpio->irq_enabled[data->hwirq] = false; ++} + +-static const struct regmap_irq_chip max77620_gpio_irq_chip = { +- .name = "max77620-gpio", +- .irqs = max77620_gpio_irqs, +- .num_irqs = ARRAY_SIZE(max77620_gpio_irqs), +- .num_regs = 1, +- .num_type_reg = 8, +- .irq_reg_stride = 1, +- .type_reg_stride = 1, +- .status_base = MAX77620_REG_IRQ_LVL2_GPIO, +- .type_base = MAX77620_REG_GPIO0, ++static void max77620_gpio_irq_unmask(struct irq_data *data) ++{ ++ struct gpio_chip *chip = irq_data_get_irq_chip_data(data); ++ struct max77620_gpio *gpio = gpiochip_get_data(chip); ++ ++ gpio->irq_enabled[data->hwirq] = true; ++} ++ ++static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type) ++{ ++ struct gpio_chip *chip = irq_data_get_irq_chip_data(data); ++ struct max77620_gpio *gpio = gpiochip_get_data(chip); ++ unsigned int irq_type; ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_RISING: ++ irq_type = MAX77620_CNFG_GPIO_INT_RISING; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ irq_type = MAX77620_CNFG_GPIO_INT_FALLING; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ irq_type = MAX77620_CNFG_GPIO_INT_RISING | ++ MAX77620_CNFG_GPIO_INT_FALLING; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ gpio->irq_type[data->hwirq] = irq_type; ++ ++ return 0; ++} ++ ++static void max77620_gpio_bus_lock(struct irq_data *data) ++{ ++ struct gpio_chip *chip = irq_data_get_irq_chip_data(data); ++ struct max77620_gpio *gpio = gpiochip_get_data(chip); ++ ++ mutex_lock(&gpio->buslock); ++} ++ ++static void max77620_gpio_bus_sync_unlock(struct irq_data *data) ++{ ++ struct gpio_chip *chip = irq_data_get_irq_chip_data(data); ++ struct max77620_gpio *gpio = gpiochip_get_data(chip); ++ unsigned int value, offset = data->hwirq; ++ int err; ++ ++ value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0; ++ ++ err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset), ++ MAX77620_CNFG_GPIO_INT_MASK, value); ++ if (err < 0) ++ dev_err(chip->parent, "failed to update interrupt mask: %d\n", ++ err); ++ ++ mutex_unlock(&gpio->buslock); ++} ++ ++static struct irq_chip max77620_gpio_irqchip = { ++ .name = "max77620-gpio", ++ .irq_mask = max77620_gpio_irq_mask, ++ .irq_unmask = max77620_gpio_irq_unmask, ++ .irq_set_type = max77620_gpio_set_irq_type, ++ .irq_bus_lock = max77620_gpio_bus_lock, ++ .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock, ++ .flags = IRQCHIP_MASK_ON_SUSPEND, + }; + + static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset) +@@ -254,14 +260,6 @@ static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset, + return -ENOTSUPP; + } + +-static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) +-{ +- struct max77620_gpio *mgpio = gpiochip_get_data(gc); +- struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent); +- +- return regmap_irq_get_virq(chip->gpio_irq_data, offset); +-} +- + static int max77620_gpio_probe(struct platform_device *pdev) + { + struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent); +@@ -287,7 +285,6 @@ static int max77620_gpio_probe(struct platform_device *pdev) + mgpio->gpio_chip.direction_output = max77620_gpio_dir_output; + mgpio->gpio_chip.set = max77620_gpio_set; + mgpio->gpio_chip.set_config = max77620_gpio_set_config; +- mgpio->gpio_chip.to_irq = max77620_gpio_to_irq; + mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR; + mgpio->gpio_chip.can_sleep = 1; + mgpio->gpio_chip.base = -1; +@@ -303,15 +300,21 @@ static int max77620_gpio_probe(struct platform_device *pdev) + return ret; + } + +- ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, gpio_irq, +- IRQF_ONESHOT, 0, +- &max77620_gpio_irq_chip, +- &chip->gpio_irq_data); ++ mutex_init(&mgpio->buslock); ++ ++ gpiochip_irqchip_add_nested(&mgpio->gpio_chip, &max77620_gpio_irqchip, ++ 0, handle_edge_irq, IRQ_TYPE_NONE); ++ ++ ret = request_threaded_irq(gpio_irq, NULL, max77620_gpio_irqhandler, ++ IRQF_ONESHOT, "max77620-gpio", mgpio); + if (ret < 0) { +- dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret); ++ dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret); + return ret; + } + ++ gpiochip_set_nested_irqchip(&mgpio->gpio_chip, &max77620_gpio_irqchip, ++ gpio_irq); ++ + return 0; + } + diff --git a/kernel.spec b/kernel.spec index bb0be106a..5ce145554 100644 --- a/kernel.spec +++ b/kernel.spec @@ -538,6 +538,10 @@ Patch308: arm64-dts-rockchip-fix-Rockpro64-RK808-interrupt-line.patch Patch320: arm64-tegra-jetson-tx1-fixes.patch # https://www.spinics.net/lists/linux-tegra/msg43110.html Patch321: arm64-tegra-Jetson-TX2-Allow-bootloader-to-configure.patch +# https://patchwork.kernel.org/patch/11171225/ +Patch322: mfd-max77620-Do-not-allocate-IRQs-upfront.patch +# https://patchwork.ozlabs.org/patch/1170631/ +Patch323: gpio-max77620-Use-correct-unit-for-debounce-times.patch # 400 - IBM (ppc/s390x) patches @@ -1757,6 +1761,9 @@ fi # # %changelog +* Sun Oct 6 2019 Peter Robinson +- Fixes for Jetson TX1/TX2 series of devices + * Fri Oct 04 2019 Jeremy Cline - 5.4.0-0.rc1.git1.1 - Linux v5.4-rc1-14-gcc3a7bfe62b9 diff --git a/mfd-max77620-Do-not-allocate-IRQs-upfront.patch b/mfd-max77620-Do-not-allocate-IRQs-upfront.patch new file mode 100644 index 000000000..0b4820ad7 --- /dev/null +++ b/mfd-max77620-Do-not-allocate-IRQs-upfront.patch @@ -0,0 +1,183 @@ +From patchwork Wed Oct 2 14:43:18 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 11171225 +Return-Path: + +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C771E1747 + for ; + Wed, 2 Oct 2019 14:45:14 +0000 (UTC) +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 9703B21D81 + for ; + Wed, 2 Oct 2019 14:45:14 +0000 (UTC) +Authentication-Results: mail.kernel.org; + dkim=pass (2048-bit key) header.d=lists.infradead.org + header.i=@lists.infradead.org header.b="LCP5OdWP"; + dkim=fail reason="signature verification failed" (2048-bit key) + header.d=gmail.com header.i=@gmail.com header.b="ahoJ80fO" +DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9703B21D81 +Authentication-Results: mail.kernel.org; + dmarc=fail (p=none dis=none) header.from=gmail.com +Authentication-Results: mail.kernel.org; + spf=none + smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20170209; h=Sender: + Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To + :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: + Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: + List-Owner; bh=csIWPoJz7RR9msf1imaCNOLXiDPcaRmxRKjOL8gMaXM=; b=LCP5OdWPpIBxJz + tSNffGBZI2pwLSarAvmqKIowLW5LghNe3CVQh7HM3sIR+IqrUtTSXi/0EEQAQORrYHSnR4zrDlubl + 8IIqIetbgOrEmYRpHQxWZV/Z0p5JTdvNVeOiR63CuFbjz/h9UXPWOiLZijU1eZfSN2UuEJWxzoWMF + CsXxW+3rZ3os8AAa9x0lt6gGLwAPEPrxP44q4AJTVp3q+cD7GTXHu0F2ZT2flxES+cFF2/cPg2GiM + yR5j7GNMDhdxFKjGp8qcDhfCKx/0jF0DofnC4JsVlN0R25HdwYHzdHhysk8ca7JxLIMJlgXsgM5aY + 4XUIEB/0CjoPtdbP+8yw==; +Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) + by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) + id 1iFfsO-0006Nf-SR; Wed, 02 Oct 2019 14:45:12 +0000 +Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) + by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) + id 1iFfqd-0003rK-EL + for linux-arm-kernel@lists.infradead.org; Wed, 02 Oct 2019 14:43:47 +0000 +Received: by mail-wr1-x443.google.com with SMTP id w12so19991081wro.5 + for ; + Wed, 02 Oct 2019 07:43:21 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=y9l/1MkRoZLCyZNPXaR5fzwvTbuyIzYA20JLtWuhYR4=; + b=ahoJ80fONPxwQPqvbuQRAba40syj0YJFK3SbqTxd0FOzhs1n3WTvNd/gHQ+2WK5WwB + 8joqipXveUGBgePR1RwHR0oQyDAumewRmSMStvhyCHPeo154CNqZfGQNlbNlRng2QJqd + 1/Sq8GNJ1DjcLifpHWbCC9LoK5U3UkvdIWHPFx0cqJ+ENvPHkYPr2FdpaZ8jxuJta3TT + dplkNk0AsL/tc33KBJbKUSlnYppX878WQXUvnhdB+TRmr5R3dtc5Ewc0TH4h7V1SXTly + GiNnbbCc+BKzzqk9PTo/Pqf5dzWcpNDBA1GUkzQZDTXOXXUzBjnlrTaQctjSdE6meWfJ + JbDw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=y9l/1MkRoZLCyZNPXaR5fzwvTbuyIzYA20JLtWuhYR4=; + b=m4CouDn44ioMScPU+9h/V5vlxCAt0m4CSZKRu3pcsThkHE6u1TeKieaoBr1mh1qnIv + YS+V9Cd7osJa8R8USg+SJkEaSSarOn4kUq2MPTgMMmvKb63SSCCs0QD44nwEBAjIgMd/ + /akFUOMTGQBnN7P8Iq3KWI00bVJLeoVWmqtQPkLFI1cIRrkCKTF4jh6b+i6xsiT8t2rd + l6WPsWnKkqUmPAqzpmLJ9bmSsiGBBFUexUJDcQnskkx6tTBzFhyNtpsbq6VdcY2mS3LR + rgGbisZRFdLvdZfGhmPX1hRgDoiHQLuWNAv49LtJtR7/CjNFmsKr4MBg1ydz0uO01Axr + zoIQ== +X-Gm-Message-State: APjAAAXPZ9a+CEGZKeL6T+FXZoBRFrxryg3xujpPFnNpjznB8ehsaTI0 + P6wL6cWqK9IRnS17Y/YRAb4= +X-Google-Smtp-Source: + APXvYqyETp8FIXhzzDrv+mhfzHhU0D9h3bcpLQ9oRbkEYPG7JvxLk5RVWx/ooYmku2+exI6oXsHTnA== +X-Received: by 2002:a5d:4dd0:: with SMTP id f16mr2905889wru.85.1570027400467; + Wed, 02 Oct 2019 07:43:20 -0700 (PDT) +Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) + by smtp.gmail.com with ESMTPSA id z125sm10251381wme.37.2019.10.02.07.43.19 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 02 Oct 2019 07:43:19 -0700 (PDT) +From: Thierry Reding +To: Lee Jones +Subject: [PATCH] mfd: max77620: Do not allocate IRQs upfront +Date: Wed, 2 Oct 2019 16:43:18 +0200 +Message-Id: <20191002144318.140365-1-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.23.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20191002_074330_018855_CC323A91 +X-CRM114-Status: GOOD ( 11.81 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, + no trust [2a00:1450:4864:20:0:0:0:443 listed in] + [list.dnswl.org] + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail + provider (thierry.reding[at]gmail.com) + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org +Content-Type: text/plain; charset="us-ascii" +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org + +From: Thierry Reding + +regmap_add_irq_chip() will try to allocate all of the IRQ descriptors +upfront if passed a non-zero irq_base parameter. However, the intention +is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0 +instead of -1 to fix that use-case. + +Signed-off-by: Thierry Reding +--- + drivers/mfd/max77620.c | 5 ++--- + include/linux/mfd/max77620.h | 1 - + 2 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c +index a851ff473a44..c7ed5c353553 100644 +--- a/drivers/mfd/max77620.c ++++ b/drivers/mfd/max77620.c +@@ -507,7 +507,6 @@ static int max77620_probe(struct i2c_client *client, + + i2c_set_clientdata(client, chip); + chip->dev = &client->dev; +- chip->irq_base = -1; + chip->chip_irq = client->irq; + chip->chip_id = (enum max77620_chip_id)id->driver_data; + +@@ -545,8 +544,8 @@ static int max77620_probe(struct i2c_client *client, + + max77620_top_irq_chip.irq_drv_data = chip; + ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, +- IRQF_ONESHOT | IRQF_SHARED, +- chip->irq_base, &max77620_top_irq_chip, ++ IRQF_ONESHOT | IRQF_SHARED, 0, ++ &max77620_top_irq_chip, + &chip->top_irq_data); + if (ret < 0) { + dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); +diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h +index 12ba157cb83f..f552ef5b1100 100644 +--- a/include/linux/mfd/max77620.h ++++ b/include/linux/mfd/max77620.h +@@ -329,7 +329,6 @@ struct max77620_chip { + struct regmap *rmap; + + int chip_irq; +- int irq_base; + + /* chip id */ + enum max77620_chip_id chip_id;