From 09074c7b2c02de5a4149d3b6dae29a68003c0c65 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Mon, 6 Jan 2020 18:50:32 +0200 Subject: [PATCH] Rebase 0002-SiFive-Unleashed-CPUFreq.patch Signed-off-by: David Abdurachmanov --- 0002-SiFive-Unleashed-CPUFreq.patch | 39 ++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/0002-SiFive-Unleashed-CPUFreq.patch b/0002-SiFive-Unleashed-CPUFreq.patch index 79c25eb01..119d6527c 100644 --- a/0002-SiFive-Unleashed-CPUFreq.patch +++ b/0002-SiFive-Unleashed-CPUFreq.patch @@ -1,9 +1,8 @@ -From 8d741d97eeb3a0c1b9aa09da15fbb1c5c7214fcd Mon Sep 17 00:00:00 2001 +From 8120ac611ab6881d6fcf31c1df02d77125434485 Mon Sep 17 00:00:00 2001 From: Fedora Kernel Team -Date: Sun, 25 Aug 2019 06:58:34 +0000 -Subject: [PATCH 2/2] SiFive Unleashed CPUFreq +Date: Mon, 6 Jan 2020 16:47:56 +0000 +Subject: [PATCH] SiFive Unleashed CPUFreq -Signed-off-by: Fedora Kernel Team --- arch/riscv/Kconfig | 8 +++++ arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++ @@ -12,10 +11,10 @@ Signed-off-by: Fedora Kernel Team 4 files changed, 52 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 441e63f..ccd590c 100644 +index a31169b..06ad604 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig -@@ -298,6 +298,14 @@ endchoice +@@ -355,6 +355,14 @@ endchoice endmenu @@ -31,10 +30,10 @@ index 441e63f..ccd590c 100644 source "kernel/power/Kconfig" diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -index 42b5ec2..b07079f 100644 +index a2e3d54..a380bc7 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -@@ -29,6 +29,7 @@ +@@ -30,6 +30,7 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; @@ -42,43 +41,43 @@ index 42b5ec2..b07079f 100644 status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; -@@ -53,6 +54,7 @@ +@@ -54,6 +55,7 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; -@@ -77,6 +79,7 @@ +@@ -78,6 +80,7 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; -@@ -101,6 +104,7 @@ +@@ -102,6 +105,7 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; -@@ -125,6 +129,7 @@ +@@ -126,6 +130,7 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -index 54fc701..5b43bdf 100644 +index 88cfcb9..e1724e3 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -@@ -40,6 +40,40 @@ +@@ -41,6 +41,40 @@ rtcclk: rtcclk { clock-frequency = ; clock-output-names = "rtcclk"; }; @@ -120,7 +119,7 @@ index 54fc701..5b43bdf 100644 &uart0 { diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig -index 3efff55..c9542a9 100644 +index e2ff95c..a2fb392 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -16,6 +16,11 @@ CONFIG_EXPERT=y @@ -136,5 +135,5 @@ index 3efff55..c9542a9 100644 CONFIG_MODULE_UNLOAD=y CONFIG_NET=y -- -2.23.0 +2.24.1