Remove non-upstream CPUFreq SiFive FU540 patch
We don't want out-of-tree patches while migrating to kernel-ark for now. We might return the patch if users ask for it (this is a popular patch). Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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From 15a265961efbd382dee76c84bae098b9ead59bab Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Sat, 21 Mar 2020 16:37:24 +0000
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Subject: [PATCH] SiFive Unleashed CPUFreq
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---
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arch/riscv/Kconfig | 8 +++++
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arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++
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.../boot/dts/sifive/hifive-unleashed-a00.dts | 34 +++++++++++++++++++
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arch/riscv/configs/defconfig | 5 +++
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4 files changed, 52 insertions(+)
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
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index 1a3b5a5..3896246 100644
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -357,6 +357,14 @@ endchoice
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endmenu
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+menu "CPU Power Management"
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+
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+source "drivers/cpuidle/Kconfig"
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+
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+source "drivers/cpufreq/Kconfig"
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+
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+endmenu
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+
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menu "Power management options"
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source "kernel/power/Kconfig"
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diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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index 7db8610..023a8fd 100644
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--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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@@ -30,6 +30,7 @@ cpu0: cpu@0 {
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -54,6 +55,7 @@ cpu1: cpu@1 {
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -78,6 +80,7 @@ cpu2: cpu@2 {
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -102,6 +105,7 @@ cpu3: cpu@3 {
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -126,6 +130,7 @@ cpu4: cpu@4 {
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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index 4a2729f..6dd6fa4 100644
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--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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@@ -46,6 +46,40 @@ gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
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};
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+
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+ fu540_c000_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-350000000 {
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+ opp-hz = /bits/ 64 <350000000>;
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+ };
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+ opp-700000000 {
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+ opp-hz = /bits/ 64 <700000000>;
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+ };
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+ opp-999999999 {
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+ opp-hz = /bits/ 64 <999999999>;
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+ };
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu1 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu2 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu3 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu4 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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};
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&uart0 {
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diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
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index c8f0842..6c47c7c 100644
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--- a/arch/riscv/configs/defconfig
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+++ b/arch/riscv/configs/defconfig
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@@ -17,6 +17,11 @@ CONFIG_BPF_SYSCALL=y
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CONFIG_SOC_SIFIVE=y
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CONFIG_SOC_VIRT=y
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CONFIG_SMP=y
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+CONFIG_CPU_IDLE=y
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+CONFIG_CPU_FREQ=y
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+CONFIG_CPU_FREQ_STAT=y
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+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
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+CONFIG_CPUFREQ_DT=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_NET=y
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--
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2.26.0.rc2
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@ -793,11 +793,6 @@ Patch76: 0001-perf-cs-etm-Move-defined-of-traceid_list.patch
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Patch77: 0001-pwm-lpss-Fix-get_state-runtime-pm-reference-handling.patch
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Patch77: 0001-pwm-lpss-Fix-get_state-runtime-pm-reference-handling.patch
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Patch78: 0001-x86-Fix-compile-issues-with-rh_check_supported.patch
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Patch78: 0001-x86-Fix-compile-issues-with-rh_check_supported.patch
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# RISC-V SiFive Unleashed CPUFreq support
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# WIP, private dev branch
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# https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
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Patch100: 0002-SiFive-Unleashed-CPUFreq.patch
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%endif
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%endif
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# empty final patch to facilitate testing of kernel patches
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# empty final patch to facilitate testing of kernel patches
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