Remove non-upstream CPUFreq SiFive FU540 patch

We don't want out-of-tree patches while migrating to kernel-ark for now.

We might return the patch if users ask for it (this is a popular patch).

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2020-05-27 09:07:46 +03:00
parent 00412356d1
commit 0734e3acf6
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
2 changed files with 0 additions and 144 deletions

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@ -1,139 +0,0 @@
From 15a265961efbd382dee76c84bae098b9ead59bab Mon Sep 17 00:00:00 2001
From: Fedora Kernel Team <kernel-team@fedoraproject.org>
Date: Sat, 21 Mar 2020 16:37:24 +0000
Subject: [PATCH] SiFive Unleashed CPUFreq
---
arch/riscv/Kconfig | 8 +++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 34 +++++++++++++++++++
arch/riscv/configs/defconfig | 5 +++
4 files changed, 52 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1a3b5a5..3896246 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -357,6 +357,14 @@ endchoice
endmenu
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+source "drivers/cpufreq/Kconfig"
+
+endmenu
+
menu "Power management options"
source "kernel/power/Kconfig"
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db8610..023a8fd 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@ cpu0: cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -54,6 +55,7 @@ cpu1: cpu@1 {
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -78,6 +80,7 @@ cpu2: cpu@2 {
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -102,6 +105,7 @@ cpu3: cpu@3 {
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -126,6 +130,7 @@ cpu4: cpu@4 {
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 4a2729f..6dd6fa4 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -46,6 +46,40 @@ gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp-999999999 {
+ opp-hz = /bits/ 64 <999999999>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu1 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu2 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu3 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu4 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
};
&uart0 {
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index c8f0842..6c47c7c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -17,6 +17,11 @@ CONFIG_BPF_SYSCALL=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPUFREQ_DT=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_NET=y
--
2.26.0.rc2

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@ -793,11 +793,6 @@ Patch76: 0001-perf-cs-etm-Move-defined-of-traceid_list.patch
Patch77: 0001-pwm-lpss-Fix-get_state-runtime-pm-reference-handling.patch
Patch78: 0001-x86-Fix-compile-issues-with-rh_check_supported.patch
# RISC-V SiFive Unleashed CPUFreq support
# WIP, private dev branch
# https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
Patch100: 0002-SiFive-Unleashed-CPUFreq.patch
%endif
# empty final patch to facilitate testing of kernel patches