81 lines
2.8 KiB
Diff
81 lines
2.8 KiB
Diff
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From 4749e0e61241cc121de572520a39dab365b9ea1d Mon Sep 17 00:00:00 2001
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From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
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Date: Thu, 8 Aug 2019 16:39:42 -0700
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Subject: usb: dwc3: Update soft-reset wait polling rate
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Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit
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will not be cleared until after all the internal clocks are synchronized
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during soft-reset. This may take a little more than 50ms. Set the
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polling rate at 20ms instead.
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Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
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Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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---
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drivers/usb/dwc3/core.c | 23 ++++++++++++++++++-----
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drivers/usb/dwc3/core.h | 2 ++
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2 files changed, 20 insertions(+), 5 deletions(-)
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diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
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index 98bce85c29d0..252c397860ef 100644
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -252,12 +252,25 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
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reg |= DWC3_DCTL_CSFTRST;
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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+ /*
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+ * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
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+ * is cleared only after all the clocks are synchronized. This can
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+ * take a little more than 50ms. Set the polling rate at 20ms
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+ * for 10 times instead.
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+ */
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+ if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
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+ retries = 10;
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+
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (!(reg & DWC3_DCTL_CSFTRST))
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goto done;
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- udelay(1);
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+ if (dwc3_is_usb31(dwc) &&
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+ dwc->revision >= DWC3_USB31_REVISION_190A)
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+ msleep(20);
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+ else
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+ udelay(1);
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} while (--retries);
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phy_exit(dwc->usb3_generic_phy);
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@@ -267,11 +280,11 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
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done:
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/*
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- * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
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- * we must wait at least 50ms before accessing the PHY domain
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- * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
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+ * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
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+ * is cleared, we must wait at least 50ms before accessing the PHY
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+ * domain (synchronization delay).
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*/
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- if (dwc3_is_usb31(dwc))
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+ if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
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msleep(50);
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return 0;
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diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
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index 3dd783b889cb..1c8b349379af 100644
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -1137,6 +1137,8 @@ struct dwc3 {
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#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
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#define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31)
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#define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31)
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+#define DWC3_USB31_REVISION_180A (0x3138302a | DWC3_REVISION_IS_DWC31)
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+#define DWC3_USB31_REVISION_190A (0x3139302a | DWC3_REVISION_IS_DWC31)
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u32 version_type;
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--
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cgit 1.2-0.3.lf.el7
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