87 lines
2.2 KiB
Diff
87 lines
2.2 KiB
Diff
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From 72fd21b62055b985d3e3fb72a1e70e3d09596174 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Sun, 27 Sep 2020 18:20:41 +0100
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Subject: [PATCH] arm64: tegra: Enable DFLL support on Jetson Nano
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Populate the DFLL node and corresponding PWM pin nodes in order to
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enable CPUFREQ support on the Jetson Nano platform.
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Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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---
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.../boot/dts/nvidia/tegra210-p3450-0000.dts | 50 +++++++++++++++----
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1 file changed, 40 insertions(+), 10 deletions(-)
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diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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index 9bc52fdb393c..4d980d753a98 100644
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--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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@@ -101,6 +101,22 @@ gpu@57000000 {
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status = "okay";
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};
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+ pinmux@700008d4 {
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+ dvfs_pwm_active_state: dvfs_pwm_active {
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+ dvfs_pwm_pbb1 {
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+ nvidia,pins = "dvfs_pwm_pbb1";
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+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
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+ };
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+ };
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+
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+ dvfs_pwm_inactive_state: dvfs_pwm_inactive {
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+ dvfs_pwm_pbb1 {
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+ nvidia,pins = "dvfs_pwm_pbb1";
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+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
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+ };
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+ };
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+ };
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+
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/* debug port */
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serial@70006000 {
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status = "okay";
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@@ -574,17 +590,31 @@ sdhci@700b0400 {
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wakeup-source;
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};
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- clocks {
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- compatible = "simple-bus";
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- #address-cells = <1>;
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- #size-cells = <0>;
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+ clock@70110000 {
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+ status = "okay";
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- clk32k_in: clock@0 {
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- compatible = "fixed-clock";
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- reg = <0>;
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- #clock-cells = <0>;
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- clock-frequency = <32768>;
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- };
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+ nvidia,cf = <6>;
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+ nvidia,ci = <0>;
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+ nvidia,cg = <2>;
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+ nvidia,droop-ctrl = <0x00000f00>;
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+ nvidia,force-mode = <1>;
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+ nvidia,sample-rate = <25000>;
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+
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+ nvidia,pwm-min-microvolts = <708000>;
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+ nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
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+ nvidia,pwm-to-pmic;
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+ nvidia,pwm-tristate-microvolts = <1000000>;
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+ nvidia,pwm-voltage-step-microvolts = <19200>;
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+
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+ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
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+ pinctrl-0 = <&dvfs_pwm_active_state>;
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+ pinctrl-1 = <&dvfs_pwm_inactive_state>;
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+ };
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+
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+ clk32k_in: clock@0 {
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ #clock-cells = <0>;
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};
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cpus {
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--
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2.26.2
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