102 lines
4.4 KiB
Diff
102 lines
4.4 KiB
Diff
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From 5fc5158c547fc3a2b46cbc6f73b926d8b78cd6e2 Mon Sep 17 00:00:00 2001
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From: "Signed-off-by: Jon Hunter" <jonathanh@nvidia.com>
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Date: Fri, 14 Feb 2020 13:53:53 +0000
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Subject: [PATCH] ARM64: tegra: Fix Tegra194 PCIe compatible string
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If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
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then this can cause the kernel to incorrectly probe the generic
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designware PCIe platform driver instead of the Tegra194 designware PCIe
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driver. This causes a boot failure on Tegra194 because the necessary
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configuration to access the hardware is not performed.
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The order in which the compatible strings are populated in Device-Tree
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is not relevant in this case, because the kernel will attempt to probe
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the device as soon as a driver is loaded and if the generic designware
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PCIe driver is loaded first, then this driver will be probed first.
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Therefore, to fix this problem, remove the "snps,dw-pcie" string from
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the compatible string as we never want this driver to be probe on
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Tegra194.
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Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
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Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
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---
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.../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 2 +-
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arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++------
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2 files changed, 7 insertions(+), 7 deletions(-)
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diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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index b739f92da58e..1f90eb39870b 100644
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--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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@@ -118,7 +118,7 @@ Tegra194:
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--------
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pcie@14180000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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index ccac43be12ac..4c58cb10fb9c 100644
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--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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@@ -1208,7 +1208,7 @@ sor3: sor@15bc0000 {
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};
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pcie@14100000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
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reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
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@@ -1253,7 +1253,7 @@ pcie@14100000 {
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};
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pcie@14120000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
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reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
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@@ -1298,7 +1298,7 @@ pcie@14120000 {
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};
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pcie@14140000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
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reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
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@@ -1343,7 +1343,7 @@ pcie@14140000 {
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};
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pcie@14160000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
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reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
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@@ -1388,7 +1388,7 @@ pcie@14160000 {
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};
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pcie@14180000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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@@ -1433,7 +1433,7 @@ pcie@14180000 {
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};
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pcie@141a0000 {
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- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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+ compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
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--
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2.24.1
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