83 lines
3.0 KiB
Diff
83 lines
3.0 KiB
Diff
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From 9c6a73c75864ad9fa49e5fa6513e4c4071c0e29f Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Mon, 8 Jan 2018 16:09:32 -0600
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Subject: [PATCH 2/2] x86/cpu/AMD: Use LFENCE_RDTSC in preference to
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MFENCE_RDTSC
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With LFENCE now a serializing instruction, use LFENCE_RDTSC in preference
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to MFENCE_RDTSC. However, since the kernel could be running under a
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hypervisor that does not support writing that MSR, read the MSR back and
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verify that the bit has been set successfully. If the MSR can be read
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and the bit is set, then set the LFENCE_RDTSC feature, otherwise set the
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MFENCE_RDTSC feature.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Tim Chen <tim.c.chen@linux.intel.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Dan Williams <dan.j.williams@intel.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
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Cc: David Woodhouse <dwmw@amazon.co.uk>
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Cc: Paul Turner <pjt@google.com>
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Link: https://lkml.kernel.org/r/20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net
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---
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arch/x86/include/asm/msr-index.h | 1 +
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arch/x86/kernel/cpu/amd.c | 18 ++++++++++++++++--
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2 files changed, 17 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index 1e7d710fef43..fa11fb1fa570 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -354,6 +354,7 @@
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#define MSR_FAM10H_NODE_ID 0xc001100c
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#define MSR_F10H_DECFG 0xc0011029
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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+#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index 5b438d81beb2..ea831c858195 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -829,6 +829,9 @@ static void init_amd(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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+ unsigned long long val;
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+ int ret;
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+
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/*
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* A serializing LFENCE has less overhead than MFENCE, so
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* use it for execution serialization. On families which
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@@ -839,8 +842,19 @@ static void init_amd(struct cpuinfo_x86 *c)
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msr_set_bit(MSR_F10H_DECFG,
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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- /* MFENCE stops RDTSC speculation */
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- set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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+ /*
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+ * Verify that the MSR write was successful (could be running
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+ * under a hypervisor) and only then assume that LFENCE is
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+ * serializing.
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+ */
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+ ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
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+ if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
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+ /* A serializing LFENCE stops RDTSC speculation */
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+ set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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+ } else {
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+ /* MFENCE stops RDTSC speculation */
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+ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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+ }
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}
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/*
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--
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2.14.3
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