2024-11-04 10:36:13 +00:00
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From patchwork Tue Feb 27 10:35:21 2024
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cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.47; Tue, 27 Feb
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2024 10:35:52 +0000
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Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn
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([fe80::5a5a:fa59:15fd:63dc]) by
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with mapi id 15.20.7270.047; Tue, 27 Feb 2024 10:35:52 +0000
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From: Minda Chen <minda.chen@starfivetech.com>
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To: Conor Dooley <conor@kernel.org>,
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=?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
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Rob Herring <robh+dt@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
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Lorenzo Pieralisi <lpieralisi@kernel.org>,
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Thomas Gleixner <tglx@linutronix.de>,
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Daire McNamara <daire.mcnamara@microchip.com>,
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Emil Renner Berthing <emil.renner.berthing@canonical.com>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
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Cc: devicetree@vger.kernel.org,
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linux-kernel@vger.kernel.org,
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linux-riscv@lists.infradead.org,
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linux-pci@vger.kernel.org,
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Paul Walmsley <paul.walmsley@sifive.com>,
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Palmer Dabbelt <palmer@dabbelt.com>,
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Albert Ou <aou@eecs.berkeley.edu>,
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Philipp Zabel <p.zabel@pengutronix.de>,
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Mason Huo <mason.huo@starfivetech.com>,
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Leyfoon Tan <leyfoon.tan@starfivetech.com>,
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Kevin Xie <kevin.xie@starfivetech.com>,
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Minda Chen <minda.chen@starfivetech.com>
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Subject: [PATCH v15,RESEND 22/23] PCI: starfive: Offload the NVMe timeout
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workaround to host drivers.
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Date: Tue, 27 Feb 2024 18:35:21 +0800
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Message-Id: <20240227103522.80915-23-minda.chen@starfivetech.com>
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In-Reply-To: <20240227103522.80915-1-minda.chen@starfivetech.com>
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References: <20240227103522.80915-1-minda.chen@starfivetech.com>
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(UTC)
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From: Kevin Xie <kevin.xie@starfivetech.com>
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As the Starfive JH7110 hardware can't keep two inbound post write in
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order all the time, such as MSI messages and NVMe completions. If the
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NVMe completion update later than the MSI, an NVMe IRQ handle will miss.
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As a workaround, we will wait a while before going to the generic
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handle here.
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Verified with NVMe SSD, USB SSD, R8169 NIC.
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The performance are stable and even higher after this patch.
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Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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---
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drivers/pci/controller/plda/pcie-plda-host.c | 12 ++++++++++++
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drivers/pci/controller/plda/pcie-plda.h | 1 +
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drivers/pci/controller/plda/pcie-starfive.c | 1 +
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3 files changed, 14 insertions(+)
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diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c
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index a18923d7cea6..9e077ddf45c0 100644
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--- a/drivers/pci/controller/plda/pcie-plda-host.c
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+++ b/drivers/pci/controller/plda/pcie-plda-host.c
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@@ -13,6 +13,7 @@
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#include <linux/msi.h>
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#include <linux/pci_regs.h>
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#include <linux/pci-ecam.h>
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+#include <linux/delay.h>
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#include "pcie-plda.h"
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@@ -44,6 +45,17 @@ static void plda_handle_msi(struct irq_desc *desc)
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bridge_base_addr + ISTATUS_LOCAL);
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status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
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for_each_set_bit(bit, &status, msi->num_vectors) {
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+ /*
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+ * As the Starfive JH7110 hardware can't keep two
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+ * inbound post write in order all the time, such as
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+ * MSI messages and NVMe completions.
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+ * If the NVMe completion update later than the MSI,
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+ * an NVMe IRQ handle will miss.
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+ * As a workaround, we will wait a while before
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+ * going to the generic handle here.
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+ */
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+ if (port->msi_quirk_delay_us)
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+ udelay(port->msi_quirk_delay_us);
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ret = generic_handle_domain_irq(msi->dev_domain, bit);
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if (ret)
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dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
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diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h
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index 04e385758a2f..feccf285dfe8 100644
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--- a/drivers/pci/controller/plda/pcie-plda.h
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+++ b/drivers/pci/controller/plda/pcie-plda.h
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@@ -186,6 +186,7 @@ struct plda_pcie_rp {
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int msi_irq;
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int intx_irq;
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int num_events;
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+ u16 msi_quirk_delay_us;
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};
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struct plda_event {
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diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
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index 9bb9f0e29565..5cfc30572b7f 100644
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--- a/drivers/pci/controller/plda/pcie-starfive.c
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+++ b/drivers/pci/controller/plda/pcie-starfive.c
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@@ -391,6 +391,7 @@ static int starfive_pcie_probe(struct platform_device *pdev)
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plda->host_ops = &sf_host_ops;
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plda->num_events = PLDA_MAX_EVENT_NUM;
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+ plda->msi_quirk_delay_us = 1;
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/* mask doorbell event */
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plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
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& ~BIT(PLDA_AXI_DOORBELL)
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