57 lines
2.0 KiB
Diff
57 lines
2.0 KiB
Diff
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From 883e2c26855e19e19bfb985221ae5a09db26a1c4 Mon Sep 17 00:00:00 2001
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From: Josh Boyer <jwboyer@obiwan.gha.chartermi.net>
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Date: Fri, 3 May 2013 17:10:32 -0400
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Subject: [PATCH] Revert "drm/i915: revert eDP bpp clamping code changes"
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This reverts commit 57c219633275c7e7413f8bc7be250dc092887458.
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---
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drivers/gpu/drm/i915/intel_dp.c | 18 ++++--------------
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1 file changed, 4 insertions(+), 14 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
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index fb2fbc1..e0ee2ca 100644
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--- a/drivers/gpu/drm/i915/intel_dp.c
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+++ b/drivers/gpu/drm/i915/intel_dp.c
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@@ -702,6 +702,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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/* Walk through all bpp values. Luckily they're all nicely spaced with 2
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* bpc in between. */
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bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
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+ if (is_edp(intel_dp) && dev_priv->edp.bpp)
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+ bpp = min_t(int, bpp, dev_priv->edp.bpp);
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+
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for (; bpp >= 6*3; bpp -= 2*3) {
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mode_rate = intel_dp_link_required(target_clock, bpp);
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@@ -739,6 +742,7 @@ found:
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intel_dp->link_bw = bws[clock];
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intel_dp->lane_count = lane_count;
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adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
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+ pipe_config->pipe_bpp = bpp;
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pipe_config->pixel_target_clock = target_clock;
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DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
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@@ -751,20 +755,6 @@ found:
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target_clock, adjusted_mode->clock,
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&pipe_config->dp_m_n);
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- /*
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- * XXX: We have a strange regression where using the vbt edp bpp value
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- * for the link bw computation results in black screens, the panel only
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- * works when we do the computation at the usual 24bpp (but still
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- * requires us to use 18bpp). Until that's fully debugged, stay
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- * bug-for-bug compatible with the old code.
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- */
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- if (is_edp(intel_dp) && dev_priv->edp.bpp) {
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- DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
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- bpp, dev_priv->edp.bpp);
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- bpp = min_t(int, bpp, dev_priv->edp.bpp);
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- }
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- pipe_config->pipe_bpp = bpp;
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-
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return true;
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}
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--
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1.8.2.1
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