100 lines
3.2 KiB
Diff
100 lines
3.2 KiB
Diff
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radeon: use max_bus_speed to activate gen2 speeds
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radeon currently uses a drm function to get the speed capabilities for
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the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard
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method of performing this detection and this patch changes it to use
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the max_bus_speed attribute.
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From: Lucas Kannebley Tavares <lucaskt at linux.vnet.ibm.com>
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Signed-off-by: Kleber Sacilotto de Souza <klebers at linux.vnet.ibm.com>
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---
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drivers/gpu/drm/radeon/evergreen.c | 10 +++-------
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drivers/gpu/drm/radeon/r600.c | 9 ++-------
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drivers/gpu/drm/radeon/rv770.c | 9 ++-------
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3 files changed, 7 insertions(+), 21 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
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index 105bafb..3966696 100644
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--- a/drivers/gpu/drm/radeon/evergreen.c
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+++ b/drivers/gpu/drm/radeon/evergreen.c
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@@ -4992,8 +4992,7 @@ void evergreen_fini(struct radeon_device *rdev)
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void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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{
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- u32 link_width_cntl, speed_cntl, mask;
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- int ret;
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+ u32 link_width_cntl, speed_cntl;
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if (radeon_pcie_gen2 == 0)
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return;
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@@ -5008,11 +5007,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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if (ASIC_IS_X2(rdev))
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return;
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- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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- if (ret != 0)
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- return;
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-
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- if (!(mask & DRM_PCIE_SPEED_50))
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+ if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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+ (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
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diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
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index 1a08008..b45e648 100644
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--- a/drivers/gpu/drm/radeon/r600.c
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+++ b/drivers/gpu/drm/radeon/r600.c
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@@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
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u16 link_cntl2;
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- u32 mask;
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- int ret;
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if (radeon_pcie_gen2 == 0)
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return;
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@@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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if (rdev->family <= CHIP_R600)
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return;
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- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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- if (ret != 0)
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- return;
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-
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- if (!(mask & DRM_PCIE_SPEED_50))
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+ if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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+ (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
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diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
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index 83f612a..a6af4aa 100644
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--- a/drivers/gpu/drm/radeon/rv770.c
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+++ b/drivers/gpu/drm/radeon/rv770.c
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@@ -2113,8 +2113,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, tmp;
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u16 link_cntl2;
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- u32 mask;
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- int ret;
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if (radeon_pcie_gen2 == 0)
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return;
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@@ -2129,11 +2127,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
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if (ASIC_IS_X2(rdev))
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return;
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- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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- if (ret != 0)
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- return;
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-
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- if (!(mask & DRM_PCIE_SPEED_50))
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+ if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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+ (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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--
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1.7.1
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