New upstream release

Added patch for upstream issue #979 "Test suite segv on arm64"
Moved jeprof util to jemalloc-devel, to give less dependencies
  on the library package, closes bz #1519586
Respun the patch removing explicit altivec usage. Not all
  ppc64 have altive

jemalloc-5.0.1.no_explicit_altivec.patch

@@ -0,0 +1,13 @@
+--- configure.orig	2017-12-14 12:15:32.517920736 +0100
++++ configure	2017-12-14 12:16:22.608660037 +0100
+@@ -6865,10 +6865,6 @@
+ 	fi
+ 	;;
+   powerpc*)
+-	cat >>confdefs.h <<_ACEOF
+-#define HAVE_ALTIVEC
+-_ACEOF
+-
+ 	CPU_SPINWAIT='__asm__ volatile("or 31,31,31")'
+ 	;;
+   *)

jemalloc.spec

@@ -1,7 +1,7 @@
 Name:           jemalloc
-Version:        4.5.0
+Version:        5.0.1
 
-Release:        4%{?dist}
+Release:        1%{?dist}
 Summary:        General-purpose scalable concurrent malloc implementation
 
 Group:          System Environment/Libraries
@@ -10,9 +10,15 @@ URL:            http://www.canonware.com/jemalloc/
 Source0:        https://github.com/jemalloc/%{name}/releases/download/%{version}/%{name}-%{version}.tar.bz2
 BuildRoot:      %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
 
+# Disable explicit altivec
+Patch4:         jemalloc-5.0.1.no_explicit_altivec.patch
+
 # No Transparent Hugepages on systems not supporting them
 Patch5:         jemalloc-4.4.0.disable_thp.patch
 
+# Upstream issue #979
+Patch6:         jemalloc_fix_test_suite_segv_aarch64.patch
+
 BuildRequires:  /usr/bin/xsltproc
 BuildRequires:  perl-generators
 %ifnarch s390 %{mips}
@@ -35,12 +41,16 @@ developing applications that use %{name}.
 %prep
 %setup -q
 
+%patch4
+
 # Disable thp on systems not supporting this, trusting that Fedora will enable
 # this on the build servers when ready for installed systems.
 %ifarch %ix86 %arm aarch64 s390x
 %define disable_thp --disable-thp
 %patch5
 %endif
+%patch6 -p1
+
 
 %build
 %ifarch %ix86
@@ -68,6 +78,7 @@ uname -a
 %configure %{?disable_thp}
 make %{?_smp_mflags}
 
+
 %check
 make check
 
@@ -91,7 +102,6 @@ rm -rf %{buildroot}
 %{_libdir}/libjemalloc.so.*
 %{_bindir}/jemalloc.sh
 %{_bindir}/jemalloc-config
-%{_bindir}/jeprof
 %{_libdir}/pkgconfig/jemalloc.pc
 %doc COPYING README VERSION
 %doc doc/jemalloc.html
@@ -99,6 +109,7 @@ rm -rf %{buildroot}
 %files devel
 %defattr(-,root,root,-)
 %{_includedir}/jemalloc
+%{_bindir}/jeprof
 %{_libdir}/libjemalloc.so
 %{_mandir}/man3/jemalloc.3*
 
@@ -107,6 +118,14 @@ rm -rf %{buildroot}
 %postun -p /sbin/ldconfig
 
 %changelog
+* Wed Dec 13 2017 Ingvar Hagelund <ingvar@redpill-linpro.com> - 5.0.1-1
+- New upstream release
+- Added patch for upstream issue #979 "Test suite segv on arm64"
+- Moved jeprof util to jemalloc-devel, to give less dependencies
+  on the library package, closes bz #1519586
+- Respun the patch removing explicit altivec usage. Not all
+  ppc64 have altive
+
 * Wed Aug 16 2017 Ingvar Hagelund <ingvar@redpill-linpro.com> - 4.5.0-4
 - Rather use ifarch than checking builder kernel for thp support
 - Cleanup; removed unnecessary patch for atomic ops on arm, pulled el5 support,

jemalloc_fix_test_suite_segv_aarch64.patch

@@ -0,0 +1,39 @@
+From 8cfc9dec37b312a2686f602bbcdd102ca07cca99 Mon Sep 17 00:00:00 2001
+From: David Goldblatt <davidgoldblatt@fb.com>
+Date: Fri, 29 Sep 2017 13:54:08 -0700
+Subject: [PATCH] ARM: Don't extend bit LG_VADDR to compute high address bits.
+
+In userspace ARM on Linux, zero-ing the high bits is the correct way to do this.
+This doesn't fix the fact that we currently set LG_VADDR to 48 on ARM, when in
+fact larger virtual address sizes are coming soon.  We'll cross that bridge when
+we come to it.
+---
+ include/jemalloc/internal/rtree.h | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/include/jemalloc/internal/rtree.h b/include/jemalloc/internal/rtree.h
+index b5d4db39..4563db23 100644
+--- a/include/jemalloc/internal/rtree.h
++++ b/include/jemalloc/internal/rtree.h
+@@ -178,9 +178,21 @@ rtree_leaf_elm_bits_read(tsdn_t *tsdn, rtree_t *rtree, rtree_leaf_elm_t *elm,
+ 
+ JEMALLOC_ALWAYS_INLINE extent_t *
+ rtree_leaf_elm_bits_extent_get(uintptr_t bits) {
++#    ifdef __aarch64__
++	/*
++	 * aarch64 doesn't sign extend the highest virtual address bit to set
++	 * the higher ones.  Instead, the high bits gets zeroed.
++	 */
++	uintptr_t high_bit_mask = ((uintptr_t)1 << LG_VADDR) - 1;
++	/* Mask off the slab bit. */
++	uintptr_t low_bit_mask = ~(uintptr_t)1;
++	uintptr_t mask = high_bit_mask & low_bit_mask;
++	return (extent_t *)(bits & mask);
++#    else
+ 	/* Restore sign-extended high bits, mask slab bit. */
+ 	return (extent_t *)((uintptr_t)((intptr_t)(bits << RTREE_NHIB) >>
+ 	    RTREE_NHIB) & ~((uintptr_t)0x1));
++#    endif
+ }
+ 
+ JEMALLOC_ALWAYS_INLINE szind_t