Add support for RISC-V (riscv64)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
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@ -0,0 +1,71 @@
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diff --git a/openjdk/common/autoconf/platform.m4 b/openjdk/common/autoconf/platform.m4
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index 0dbf74cbe..dcf3f747b 100644
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--- a/openjdk/common/autoconf/platform.m4
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+++ b/openjdk/common/autoconf/platform.m4
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@@ -96,6 +96,18 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU],
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VAR_CPU_BITS=64
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VAR_CPU_ENDIAN=big
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;;
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+ riscv32)
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+ VAR_CPU=riscv32
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+ VAR_CPU_ARCH=riscv
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+ VAR_CPU_BITS=32
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+ VAR_CPU_ENDIAN=little
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+ ;;
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+ riscv64)
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+ VAR_CPU=riscv64
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+ VAR_CPU_ARCH=riscv
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+ VAR_CPU_BITS=64
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+ VAR_CPU_ENDIAN=little
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+ ;;
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*)
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AC_MSG_ERROR([unsupported cpu $1])
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;;
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diff --git a/openjdk/hotspot/src/os/linux/vm/os_linux.cpp b/openjdk/hotspot/src/os/linux/vm/os_linux.cpp
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index bcce508e0..6e2659d12 100644
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--- a/openjdk/hotspot/src/os/linux/vm/os_linux.cpp
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+++ b/openjdk/hotspot/src/os/linux/vm/os_linux.cpp
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@@ -1743,6 +1743,9 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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#ifndef EM_AARCH64
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#define EM_AARCH64 183 /* ARM AARCH64 */
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#endif
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+#ifndef EM_RISCV
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+ #define EM_RISCV 243 /* RISC-V */
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+#endif
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static const arch_t arch_array[]={
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{EM_386, EM_386, ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},
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@@ -1766,6 +1769,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
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{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
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{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
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+ {EM_RISCV, EM_RISCV, ELFCLASSNONE, ELFDATA2MSB, (char*)"RISC-V"},
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};
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#if (defined IA32)
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@@ -1798,9 +1802,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_MIPS;
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#elif (defined M68K)
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static Elf32_Half running_arch_code=EM_68K;
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+#elif (defined __riscv)
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+ static Elf32_Half running_arch_code=EM_RISCV;
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#else
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#error Method os::dll_load requires that one of following is defined:\
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- AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, __sparc
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+ AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, __sparc, __riscv
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#endif
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// Identify compatability class for VM's architecture and library's architecture
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@@ -1833,10 +1839,12 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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}
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#ifndef S390
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+#ifndef __riscv
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if (lib_arch.elf_class != arch_array[running_arch_index].elf_class) {
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::snprintf(diag_msg_buf, diag_msg_max_length-1," (Possible cause: architecture word width mismatch)");
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return NULL;
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}
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+#endif // !__riscv
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#endif // !S390
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if (lib_arch.compat_class != arch_array[running_arch_index].compat_class) {
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@ -113,6 +113,9 @@
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%ifarch %{aarch64}
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%ifarch %{aarch64}
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%global archinstall aarch64
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%global archinstall aarch64
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%endif
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%endif
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%ifarch riscv64
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%global archinstall riscv64
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%endif
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# 32 bit sparc, optimized for v9
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# 32 bit sparc, optimized for v9
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%ifarch sparcv9
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%ifarch sparcv9
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%global archinstall sparc
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%global archinstall sparc
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@ -853,7 +856,7 @@ Provides: java-%{javaver}-%{origin}-accessiblity = %{epoch}:%{version}-%{release
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Name: java-%{majorver}-%{origin}
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Name: java-%{majorver}-%{origin}
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Version: %{newjavaver}.%{buildver}
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Version: %{newjavaver}.%{buildver}
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Release: 6%{?dist}
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Release: 6.0.riscv64%{?dist}
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# java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons,
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# java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons,
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# and this change was brought into RHEL-4. java-1.5.0-ibm packages
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# and this change was brought into RHEL-4. java-1.5.0-ibm packages
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# also included the epoch in their virtual provides. This created a
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# also included the epoch in their virtual provides. This created a
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@ -903,6 +906,10 @@ Source13: TestCryptoLevel.java
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# Ensure ECDSA is working
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# Ensure ECDSA is working
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Source14: TestECDSA.java
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Source14: TestECDSA.java
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# New versions of config files with RISC-V (riscv64) support.
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Source100: config.guess
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Source101: config.sub
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# RPM/distribution specific patches
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# RPM/distribution specific patches
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# Ignore AWTError when assistive technologies are loaded
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# Ignore AWTError when assistive technologies are loaded
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@ -927,6 +934,7 @@ Patch101: sorted-diff.patch
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Patch102: java-1.9.0-openjdk-size_t.patch
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Patch102: java-1.9.0-openjdk-size_t.patch
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Patch103: hotspot-min-max-macros.patch
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Patch103: hotspot-min-max-macros.patch
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Patch104: bootcycle_jobs.patch
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Patch104: bootcycle_jobs.patch
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Patch105: java-9-openjdk-riscv64.patch
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#Patch300: jstack-pr1845.patch
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#Patch300: jstack-pr1845.patch
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@ -1224,6 +1232,10 @@ if [ $prioritylength -ne 7 ] ; then
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fi
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fi
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cp %{SOURCE2} .
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cp %{SOURCE2} .
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# Update config.{guess,sub} with RISC-V (riscv64) support
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cp %{SOURCE100} openjdk/common/autoconf/build-aux/
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cp %{SOURCE101} openjdk/common/autoconf/build-aux/
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# OpenJDK patches
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# OpenJDK patches
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# Remove libraries that are linked
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# Remove libraries that are linked
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@ -1246,6 +1258,9 @@ sh %{SOURCE12}
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#%patch103 -p1
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#%patch103 -p1
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%patch104 -p1
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%patch104 -p1
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# Add support for RISC-V (riscv64)
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%patch105 -p2
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# Zero PPC fixes.
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# Zero PPC fixes.
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# TODO: propose them upstream
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# TODO: propose them upstream
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%patch400 -p1
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%patch400 -p1
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@ -1315,7 +1330,7 @@ export NUM_PROC=${NUM_PROC:-1}
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[ ${NUM_PROC} -gt %{?_smp_ncpus_max} ] && export NUM_PROC=%{?_smp_ncpus_max}
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[ ${NUM_PROC} -gt %{?_smp_ncpus_max} ] && export NUM_PROC=%{?_smp_ncpus_max}
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%endif
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%endif
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%ifarch s390x sparc64 alpha %{power64} %{aarch64}
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%ifarch s390x sparc64 alpha %{power64} %{aarch64} riscv64
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export ARCH_DATA_MODEL=64
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export ARCH_DATA_MODEL=64
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%endif
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%endif
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%ifarch alpha
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%ifarch alpha
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@ -1840,6 +1855,9 @@ require "copy_jdk_configs.lua"
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%changelog
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%changelog
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* Wed Sep 19 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 1:9.0.4.11-6.0.riscv64
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- Add support for RISC-V (riscv64)
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* Tue Feb 13 2018 Sandro Mani <manisandro@gmail.com> - 1:9.0.4.11-6
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* Tue Feb 13 2018 Sandro Mani <manisandro@gmail.com> - 1:9.0.4.11-6
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- Rebuild (giflib)
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- Rebuild (giflib)
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