Add support for RISC-V (riscv64)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
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@ -0,0 +1,71 @@
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diff --git a/openjdk/make/autoconf/platform.m4 b/openjdk/make/autoconf/platform.m4
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index e06c11af0..e1c55bb1b 100644
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--- a/openjdk/make/autoconf/platform.m4
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+++ b/openjdk/make/autoconf/platform.m4
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@@ -150,6 +150,18 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU],
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VAR_CPU_BITS=64
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VAR_CPU_ENDIAN=big
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;;
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+ riscv32)
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+ VAR_CPU=riscv32
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+ VAR_CPU_ARCH=riscv
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+ VAR_CPU_BITS=32
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+ VAR_CPU_ENDIAN=little
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+ ;;
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+ riscv64)
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+ VAR_CPU=riscv64
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+ VAR_CPU_ARCH=riscv
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+ VAR_CPU_BITS=64
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+ VAR_CPU_ENDIAN=little
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+ ;;
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*)
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AC_MSG_ERROR([unsupported cpu $1])
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;;
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diff --git a/openjdk/src/hotspot/os/linux/os_linux.cpp b/openjdk/src/hotspot/os/linux/os_linux.cpp
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index 8496e3db1..a154fd3e3 100644
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--- a/openjdk/src/hotspot/os/linux/os_linux.cpp
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+++ b/openjdk/src/hotspot/os/linux/os_linux.cpp
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@@ -1728,6 +1728,9 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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#ifndef EM_AARCH64
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#define EM_AARCH64 183 /* ARM AARCH64 */
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#endif
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+#ifndef EM_RISCV
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+ #define EM_RISCV 243 /* RISC-V */
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+#endif
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static const arch_t arch_array[]={
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{EM_386, EM_386, ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},
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@@ -1753,6 +1756,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
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{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
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{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
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+ {EM_RISCV, EM_RISCV, ELFCLASSNONE, ELFDATA2MSB, (char*)"RISC-V"},
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};
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#if (defined IA32)
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@@ -1787,9 +1791,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_68K;
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#elif (defined SH)
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static Elf32_Half running_arch_code=EM_SH;
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+#elif (defined __riscv)
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+ static Elf32_Half running_arch_code=EM_RISCV;
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#else
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#error Method os::dll_load requires that one of following is defined:\
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- AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc
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+ AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc, __riscv
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#endif
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// Identify compatability class for VM's architecture and library's architecture
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@@ -1822,10 +1828,12 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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}
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#ifndef S390
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+#ifndef __riscv
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if (lib_arch.elf_class != arch_array[running_arch_index].elf_class) {
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::snprintf(diag_msg_buf, diag_msg_max_length-1," (Possible cause: architecture word width mismatch)");
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return NULL;
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}
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+#endif // !__riscv
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#endif // !S390
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if (lib_arch.compat_class != arch_array[running_arch_index].compat_class) {
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@ -272,6 +272,10 @@
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%global archinstall aarch64
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%global stapinstall arm64
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%endif
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%ifarch riscv64
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%global archinstall riscv64
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%global stapinstall %{nil}
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%endif
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# 32 bit sparc, optimized for v9
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%ifarch sparcv9
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%global archinstall sparc
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@ -1189,6 +1193,10 @@ Source15: TestSecurityProperties.java
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# Ensure vendor settings are correct
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Source16: CheckVendor.java
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# New versions of config files with RISC-V (riscv64) support.
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Source100: config.guess
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Source101: config.sub
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############################################
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#
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# RPM/distribution specific patches
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@ -1230,6 +1238,9 @@ Patch4: pr3694-rh1340845-support_fedora_rhel_system_crypto_policy.patch
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# PR3695: Allow use of system crypto policy to be disabled by the user
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Patch7: pr3695-toggle_system_crypto_policy.patch
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# RISC-V (riscv64) support
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Patch30: java-11-openjdk-riscv64.patch
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#############################################
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#
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# Patches appearing in 11.0.10
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@ -1584,6 +1595,12 @@ if [ $prioritylength -ne 8 ] ; then
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exit 14
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fi
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%ifarch riscv64
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# Update config.{guess,sub} with RISC-V (riscv64) support
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cp %{SOURCE100} openjdk/make/autoconf/build-aux/
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cp %{SOURCE101} openjdk/make/autoconf/build-aux/
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%endif
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# OpenJDK patches
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# Remove libraries that are linked by both static and dynamic builds
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sh %{SOURCE12} %{top_level_dir_name}
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@ -1595,6 +1612,9 @@ pushd %{top_level_dir_name}
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%patch3 -p1
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%patch4 -p1
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%patch7 -p1
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%ifarch riscv64
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%patch30 -p2
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%endif
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popd # openjdk
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%patch1000
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@ -1661,7 +1681,7 @@ export NUM_PROC=${NUM_PROC:-1}
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[ ${NUM_PROC} -gt %{?_smp_ncpus_max} ] && export NUM_PROC=%{?_smp_ncpus_max}
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%endif
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%ifarch s390x sparc64 alpha %{power64} %{aarch64}
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%ifarch s390x sparc64 alpha %{power64} %{aarch64} riscv64
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export ARCH_DATA_MODEL=64
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%endif
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%ifarch alpha
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@ -2291,6 +2311,9 @@ require "copy_jdk_configs.lua"
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%endif
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%changelog
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* Fri May 07 2021 David Abdurachmanov <david.abdurachmanov@gmail.com> - 1:11.0.11.0.9-1.0.riscv64
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- Add support for RISC-V (riscv64)
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* Fri Apr 29 2021 Jiri Vanek <jvanek@redhat.com> - 1:11.0.11.0.9-1
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- adapted to debug handling in newer cjc
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- The rest of the "rpm 4.17" patch must NOT be backported, as on rpm 4.16 and down, it would casue double execution
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