Rebase riscv64 patch

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2020-04-03 10:16:57 +03:00
parent ff4d3d8eee
commit 9841b4d7e2
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
1 changed files with 2 additions and 15 deletions

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@ -21,24 +21,11 @@ index 4ad7680..6da10fc 100644
_AS_ECHO_N([(blacklisted) ])
as_cv_unaligned_access=no
;;
diff --git a/gst/gstconfig.h.in b/gst/gstconfig.h.in
index 6351c04..33dfed1 100644
--- a/gst/gstconfig.h.in
+++ b/gst/gstconfig.h.in
@@ -104,7 +104,7 @@
* http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6
* https://software.intel.com/en-us/node/583402
*/
-#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__)
+#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv)
# define GST_HAVE_UNALIGNED_ACCESS 0
#elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__)
# define GST_HAVE_UNALIGNED_ACCESS 1
diff --git a/meson.build b/meson.build
index e6e315b..e4dc8b8 100644
index 0442535..3dfc8f5 100644
--- a/meson.build
+++ b/meson.build
@@ -122,6 +122,7 @@ host_defines = [
@@ -169,6 +169,7 @@ host_defines = [
[ 'hppa', 'HAVE_CPU_HPPA' ],
[ 'm68k', 'HAVE_CPU_M68K' ],
[ 's390', 'HAVE_CPU_S390' ],