Add support for RISC-V (riscv64)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
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@ -0,0 +1,48 @@
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diff --git a/common/m4/gst-arch.m4 b/common/m4/gst-arch.m4
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index 4ad7680..6da10fc 100644
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--- a/common/m4/gst-arch.m4
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+++ b/common/m4/gst-arch.m4
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@@ -81,6 +81,9 @@ AC_DEFUN([AG_GST_ARCH],
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xcrisv32)
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HAVE_CPU_CRISV32=yes
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AC_DEFINE(HAVE_CPU_CRISV32, 1, [Define if the target CPU is a CRISv32]) ;;
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+ xriscv64)
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+ HAVE_CPU_RISCV64=yes
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+ AC_DEFINE(HAVE_CPU_RISCV64, 1, [Define if the target CPU is RISCV64]) ;;
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esac
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dnl Determine endianness
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@@ -111,7 +114,7 @@ AC_DEFUN([AG_GST_UNALIGNED_ACCESS], [
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AC_MSG_CHECKING([if unaligned memory access works correctly])
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if test x"$as_cv_unaligned_access" = x ; then
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case $host in
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- alpha*|arc*|arm*|aarch64*|hp*|mips*|sh*|sparc*|ia64*)
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+ alpha*|arc*|arm*|aarch64*|hp*|mips*|sh*|sparc*|ia64*|riscv*)
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_AS_ECHO_N([(blacklisted) ])
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as_cv_unaligned_access=no
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;;
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diff --git a/gst/gstconfig.h.in b/gst/gstconfig.h.in
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index 6351c04..33dfed1 100644
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--- a/gst/gstconfig.h.in
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+++ b/gst/gstconfig.h.in
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@@ -104,7 +104,7 @@
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* http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6
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* https://software.intel.com/en-us/node/583402
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*/
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-#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__)
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+#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv)
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# define GST_HAVE_UNALIGNED_ACCESS 0
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#elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__)
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# define GST_HAVE_UNALIGNED_ACCESS 1
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diff --git a/meson.build b/meson.build
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index e6e315b..e4dc8b8 100644
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--- a/meson.build
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+++ b/meson.build
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@@ -122,6 +122,7 @@ host_defines = [
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[ 'hppa', 'HAVE_CPU_HPPA' ],
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[ 'm68k', 'HAVE_CPU_M68K' ],
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[ 's390', 'HAVE_CPU_S390' ],
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+ [ 'riscv64', 'HAVE_CPU_RISCV64' ],
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]
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foreach h : host_defines
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if h.get(0) == host_machine.cpu()
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@ -10,7 +10,7 @@
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Name: gstreamer1
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Version: 1.14.1
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Release: 5%{?gitcommit:.git%{shortcommit}}%{?dist}
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Release: 5%{?gitcommit:.git%{shortcommit}}.0.riscv64%{?dist}
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Summary: GStreamer streaming media framework runtime
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License: LGPLv2+
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@ -24,6 +24,7 @@ Source0: http://gstreamer.freedesktop.org/src/gstreamer/gstreamer-%{versi
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%endif
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## For GStreamer RPM provides
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Patch0: gstreamer-inspect-rpm-format.patch
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Patch1: gstreamer-add-riscv64.patch
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Source1: gstreamer1.prov
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Source2: gstreamer1.attr
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@ -91,6 +92,7 @@ GStreamer streaming media framework.
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%prep
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%setup -q -n gstreamer-%{version}
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%patch0 -p1 -b .rpm-provides
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%patch1 -p1 -b .riscv64
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%build
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NOCONFIGURE=1 \
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@ -201,6 +203,9 @@ install -m0644 -D %{SOURCE2} $RPM_BUILD_ROOT%{_rpmconfigdir}/fileattrs/gstreamer
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%changelog
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* Tue Jun 19 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 1.14.1-5.0.riscv64
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- Add support for RISC-V (riscv64)
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* Fri Jun 15 2018 Wim Taymans <wtaymans@redhat.com> - 1.14.1-5
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- Remove xfig build dependency. It has not been needed since
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version 1.2.0
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