b68cfb3330
Upstream commit: b2f32e746492615a6eb3e66fac1e766e32e8deb1
- malloc: Simplify implementation of __malloc_assert
- Update syscall-names.list for Linux 5.18
- x86: Add missing IS_IN (libc) check to strncmp-sse4_2.S
- x86: Move mem{p}{mov|cpy}_{chk_}erms to its own file
- x86: Move and slightly improve memset_erms
- x86: Add definition for __wmemset_chk AVX2 RTM in ifunc impl list
- x86: Put wcs{n}len-sse4.1 in the sse4.1 text section
- x86: Align entry for memrchr to 64-bytes.
- x86: Add BMI1/BMI2 checks for ISA_V3 check
- x86: Cleanup bounds checking in large memcpy case
- x86: Add bounds `x86_non_temporal_threshold`
- x86: Add sse42 implementation to strcmp's ifunc
- x86: Fix misordered logic for setting `rep_movsb_stop_threshold`
- x86: Align varshift table to 32-bytes
- x86: ZERO_UPPER_VEC_REGISTERS_RETURN_XTEST expect no transactions
- x86: Shrink code size of memchr-evex.S
- x86: Shrink code size of memchr-avx2.S
- x86: Optimize memrchr-avx2.S
- x86: Optimize memrchr-evex.S
- x86: Optimize memrchr-sse2.S
- x86: Add COND_VZEROUPPER that can replace vzeroupper if no `ret`
- x86: Create header for VEC classes in x86 strings library
- x86_64: Add strstr function with 512-bit EVEX
- x86-64: Ignore r_addend for R_X86_64_GLOB_DAT/R_X86_64_JUMP_SLOT
- x86_64: Implement evex512 version of strlen, strnlen, wcslen and wcsnlen
- x86_64: Remove bzero optimization
- x86_64: Remove end of line trailing spaces
- nptl: Fix ___pthread_unregister_cancel_restore asynchronous restore
- linux: Fix mq_timereceive check for 32 bit fallback code (BZ 29304)
57 lines
2.5 KiB
Diff
57 lines
2.5 KiB
Diff
commit 6e008c884dad5a25f91085c68d044bb5e2d63761
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Author: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Tue Jun 14 13:50:11 2022 -0700
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x86: Fix misordered logic for setting `rep_movsb_stop_threshold`
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Move the setting of `rep_movsb_stop_threshold` to after the tunables
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have been collected so that the `rep_movsb_stop_threshold` (which
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is used to redirect control flow to the non_temporal case) will
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use any user value for `non_temporal_threshold` (set using
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glibc.cpu.x86_non_temporal_threshold)
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(cherry picked from commit 035591551400cfc810b07244a015c9411e8bff7c)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 2e43e67e4f4037d3..560bf260e8fbd7bf 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -898,18 +898,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (CPU_FEATURE_USABLE_P (cpu_features, FSRM))
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rep_movsb_threshold = 2112;
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- unsigned long int rep_movsb_stop_threshold;
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- /* ERMS feature is implemented from AMD Zen3 architecture and it is
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- performing poorly for data above L2 cache size. Henceforth, adding
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- an upper bound threshold parameter to limit the usage of Enhanced
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- REP MOVSB operations and setting its value to L2 cache size. */
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- if (cpu_features->basic.kind == arch_kind_amd)
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- rep_movsb_stop_threshold = core;
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- /* Setting the upper bound of ERMS to the computed value of
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- non-temporal threshold for architectures other than AMD. */
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- else
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- rep_movsb_stop_threshold = non_temporal_threshold;
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-
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/* The default threshold to use Enhanced REP STOSB. */
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unsigned long int rep_stosb_threshold = 2048;
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@@ -951,6 +939,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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SIZE_MAX);
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#endif
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+ unsigned long int rep_movsb_stop_threshold;
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+ /* ERMS feature is implemented from AMD Zen3 architecture and it is
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+ performing poorly for data above L2 cache size. Henceforth, adding
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+ an upper bound threshold parameter to limit the usage of Enhanced
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+ REP MOVSB operations and setting its value to L2 cache size. */
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+ if (cpu_features->basic.kind == arch_kind_amd)
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+ rep_movsb_stop_threshold = core;
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+ /* Setting the upper bound of ERMS to the computed value of
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+ non-temporal threshold for architectures other than AMD. */
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+ else
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+ rep_movsb_stop_threshold = non_temporal_threshold;
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+
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cpu_features->data_cache_size = data;
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cpu_features->shared_cache_size = shared;
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cpu_features->non_temporal_threshold = non_temporal_threshold;
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