8377b8e913
- Increase size of temporary buffers to avoid unnecessary DNS
lookups (#837695)
- Fix gcc_asset failure in _Unwind_SetSpColumn() on ppc64. (#852445)
- Don't free memory allocated by mempool allocator (#863453)
106 lines
4.3 KiB
Diff
106 lines
4.3 KiB
Diff
From libc-alpha-return-31329-listarch-libc-alpha=sources dot redhat dot com at sourceware dot org Wed Jul 11 11:36:39 2012
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X-Spam-Check-By: sourceware.org
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Date: Wed, 11 Jul 2012 21:06:06 +0930
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From: Alan Modra <amodra at gmail dot com>
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To: libc-alpha at sourceware dot org
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Cc: rsa at linux dot vnet dot ibm dot com
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Subject: powerpc pthread_once bug fix
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Message-ID: <20120711113606.GM3117@bubble.grove.modra.org>
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MIME-Version: 1.0
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Content-Type: text/plain; charset=us-ascii
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User-Agent: Mutt/1.5.21 (2010-09-15)
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Mailing-List: contact libc-alpha-help at sourceware dot org; run by ezmlm
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Precedence: bulk
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List-Id: <libc-alpha.sourceware.org>
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Sender: libc-alpha-owner at sourceware dot org
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Delivered-To: mailing list libc-alpha at sourceware dot org
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This fixes some bugs in the powerpc pthread_once code. Ref
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gcc.gnu.org/bugzilla/show_bug.cgi?id=52839#c10
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Release barriers are needed to ensure any memory written by
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init_routine is seen by other threads before *once_control changes.
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In the case of clear_once_control we need to flush any partially
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written state.
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2012-06-28 Alan Modra <amodra@gmail.com>
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* sysdeps/unix/sysv/linux/powerpc/pthread_once.c (__pthread_once):
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Add release barrier before setting once_control to say
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initialisation is done. Add hints on lwarx. Use macro in
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place of isync.
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(clear_once_control): Add release barrier.
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[ This was slightly edited -- the constraint for operand 0 in the last asm was changed
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from "=&r" to "=&b" as using r0 in that context results in a load immediate 1 into
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the target rather than incrementing the target. ]
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diff --git a/nptl/sysdeps/unix/sysv/linux/powerpc/pthread_once.c b/nptl/sysdeps/unix/sysv/linux/powerpc/pthread_once.c
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index 4e3d7bd..bb1ebf2 100644
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--- a/nptl/sysdeps/unix/sysv/linux/powerpc/pthread_once.c
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+++ b/nptl/sysdeps/unix/sysv/linux/powerpc/pthread_once.c
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@@ -28,6 +28,7 @@ clear_once_control (void *arg)
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{
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pthread_once_t *once_control = (pthread_once_t *) arg;
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+ __asm __volatile (__lll_rel_instr);
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*once_control = 0;
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lll_futex_wake (once_control, INT_MAX, LLL_PRIVATE);
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}
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@@ -47,15 +48,15 @@ __pthread_once (pthread_once_t *once_control, void (*init_routine) (void))
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oldval = *once_control;
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if ((oldval & 2) == 0)
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*once_control = newval;
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- Do this atomically.
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+ Do this atomically with an acquire barrier.
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*/
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newval = __fork_generation | 1;
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- __asm __volatile ("1: lwarx %0,0,%3\n"
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+ __asm __volatile ("1: lwarx %0,0,%3" MUTEX_HINT_ACQ "\n"
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" andi. %1,%0,2\n"
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" bne 2f\n"
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" stwcx. %4,0,%3\n"
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" bne 1b\n"
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- "2: isync"
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+ "2: " __lll_acq_instr
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: "=&r" (oldval), "=&r" (tmp), "=m" (*once_control)
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: "r" (once_control), "r" (newval), "m" (*once_control)
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: "cr0");
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@@ -87,8 +88,18 @@ __pthread_once (pthread_once_t *once_control, void (*init_routine) (void))
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pthread_cleanup_pop (0);
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- /* Add one to *once_control to take the bottom 2 bits from 01 to 10. */
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- atomic_increment (once_control);
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+ /* Add one to *once_control to take the bottom 2 bits from 01 to 10.
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+ A release barrier is needed to ensure memory written by init_routine
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+ is seen in other threads before *once_control changes. */
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+ int tmp;
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+ __asm __volatile (__lll_rel_instr "\n"
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+ "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n"
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+ " addi %0,%0,1\n"
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+ " stwcx. %0,0,%2\n"
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+ " bne- 1b"
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+ : "=&b" (tmp), "=m" (*once_control)
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+ : "r" (once_control), "m" (*once_control)
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+ : "cr0");
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/* Wake up all other threads. */
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lll_futex_wake (once_control, INT_MAX, LLL_PRIVATE);
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--
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Alan Modra
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Australia Development Lab, IBM
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