Revert aarch64 memset changes (cec3aef3241cec3aef32412779e) (#2327564)
This commit is contained in:
Florian Weimer
parent
0e9c278a7e
commit
88d869c1c2
158
glibc-rh2327564-1.patch
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158
glibc-rh2327564-1.patch
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@ -0,0 +1,158 @@
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commit d115e98ad627fae62679bc18e3bf062a898860cb
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Author: Florian Weimer <fweimer@redhat.com>
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Date: Wed Nov 20 19:21:45 2024 +0100
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Revert "AArch64: Remove memset-reg.h"
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This reverts commit 8ecb477ea16a387a44ace5bf59d39a7e270b238b.
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diff --git a/sysdeps/aarch64/memset-reg.h b/sysdeps/aarch64/memset-reg.h
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new file mode 100644
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index 0000000000000000..6c7f60b37edf3b11
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--- /dev/null
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+++ b/sysdeps/aarch64/memset-reg.h
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@@ -0,0 +1,30 @@
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+/* Register aliases for memset to be used across implementations.
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+ Copyright (C) 2017-2024 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <https://www.gnu.org/licenses/>. */
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+
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+#define dstin x0
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+#define val x1
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+#define valw w1
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+#define count x2
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+#define dst x3
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+#define dstend x4
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+#define tmp1 x5
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+#define tmp1w w5
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+#define tmp2 x6
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+#define tmp2w w6
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+#define zva_len x7
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+#define zva_lenw w7
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diff --git a/sysdeps/aarch64/memset.S b/sysdeps/aarch64/memset.S
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index b76dde1557ed8fb1..caafb019e2b6217b 100644
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--- a/sysdeps/aarch64/memset.S
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+++ b/sysdeps/aarch64/memset.S
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@@ -30,6 +30,7 @@
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*/
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#define dstin x0
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+#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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diff --git a/sysdeps/aarch64/multiarch/memset_a64fx.S b/sysdeps/aarch64/multiarch/memset_a64fx.S
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index f665b5a891433c1c..2e6d882fc931a882 100644
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--- a/sysdeps/aarch64/multiarch/memset_a64fx.S
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+++ b/sysdeps/aarch64/multiarch/memset_a64fx.S
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@@ -18,6 +18,7 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include <sysdeps/aarch64/memset-reg.h>
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/* Assumptions:
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*
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@@ -35,14 +36,6 @@
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.arch armv8.2-a+sve
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-#define dstin x0
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-#define valw w1
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-#define count x2
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-#define dst x3
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-#define dstend x4
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-#define tmp1 x5
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-#define tmp2 x6
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-
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.macro st1b_unroll first=0, last=7
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st1b z0.b, p0, [dst, \first, mul vl]
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.if \last-\first
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diff --git a/sysdeps/aarch64/multiarch/memset_emag.S b/sysdeps/aarch64/multiarch/memset_emag.S
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index cf1b25f2edf64900..6d714ed0e1b396ef 100644
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--- a/sysdeps/aarch64/multiarch/memset_emag.S
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+++ b/sysdeps/aarch64/multiarch/memset_emag.S
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@@ -18,6 +18,7 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include "memset-reg.h"
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/* Assumptions:
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*
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@@ -25,13 +26,6 @@
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*
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*/
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-#define dstin x0
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-#define val x1
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-#define valw w1
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-#define count x2
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-#define dst x3
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-#define dstend x4
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-
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ENTRY (__memset_emag)
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PTR_ARG (0)
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diff --git a/sysdeps/aarch64/multiarch/memset_kunpeng.S b/sysdeps/aarch64/multiarch/memset_kunpeng.S
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index f815c20b0383f057..7b215501376cbe03 100644
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--- a/sysdeps/aarch64/multiarch/memset_kunpeng.S
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+++ b/sysdeps/aarch64/multiarch/memset_kunpeng.S
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@@ -18,6 +18,7 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include <sysdeps/aarch64/memset-reg.h>
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/* Assumptions:
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*
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@@ -25,12 +26,6 @@
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*
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*/
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-#define dstin x0
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-#define valw w1
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-#define count x2
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-#define dst x3
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-#define dstend x4
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-
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ENTRY (__memset_kunpeng)
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PTR_ARG (0)
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diff --git a/sysdeps/aarch64/multiarch/memset_oryon1.S b/sysdeps/aarch64/multiarch/memset_oryon1.S
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index 6fa28a9bd030a705..b43a43b54e1b3439 100644
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--- a/sysdeps/aarch64/multiarch/memset_oryon1.S
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+++ b/sysdeps/aarch64/multiarch/memset_oryon1.S
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@@ -19,18 +19,12 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include "memset-reg.h"
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/* Assumptions:
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ARMv8-a, AArch64, unaligned accesses
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*/
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-#define dstin x0
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-#define val x1
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-#define valw w1
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-#define count x2
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-#define dst x3
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-#define dstend x4
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-
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ENTRY (__memset_oryon1)
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PTR_ARG (0)
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276
glibc-rh2327564-2.patch
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276
glibc-rh2327564-2.patch
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@ -0,0 +1,276 @@
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commit b26c53ecc4dd3bc48b11e09f6ddc7c1441e126c2
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Author: Florian Weimer <fweimer@redhat.com>
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Date: Wed Nov 20 19:21:48 2024 +0100
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Revert "AArch64: Optimize memset"
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This reverts commit cec3aef32412779e207f825db0d057ebb4628ae8.
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diff --git a/sysdeps/aarch64/memset.S b/sysdeps/aarch64/memset.S
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index caafb019e2b6217b..7ef77ee8c926de21 100644
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--- a/sysdeps/aarch64/memset.S
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+++ b/sysdeps/aarch64/memset.S
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@@ -1,5 +1,4 @@
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-/* Generic optimized memset using SIMD.
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- Copyright (C) 2012-2024 Free Software Foundation, Inc.
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+/* Copyright (C) 2012-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@@ -18,6 +17,7 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include "memset-reg.h"
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#ifndef MEMSET
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# define MEMSET memset
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@@ -25,132 +25,130 @@
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/* Assumptions:
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*
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- * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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+ * ARMv8-a, AArch64, unaligned accesses
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*
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*/
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-#define dstin x0
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-#define val x1
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-#define valw w1
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-#define count x2
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-#define dst x3
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-#define dstend x4
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-#define zva_val x5
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-#define off x3
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-#define dstend2 x5
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-
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ENTRY (MEMSET)
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+
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PTR_ARG (0)
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SIZE_ARG (2)
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dup v0.16B, valw
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- cmp count, 16
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- b.lo L(set_small)
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-
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add dstend, dstin, count
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- cmp count, 64
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- b.hs L(set_128)
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- /* Set 16..63 bytes. */
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- mov off, 16
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- and off, off, count, lsr 1
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- sub dstend2, dstend, off
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- str q0, [dstin]
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- str q0, [dstin, off]
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- str q0, [dstend2, -16]
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- str q0, [dstend, -16]
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- ret
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+ cmp count, 96
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+ b.hi L(set_long)
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+ cmp count, 16
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+ b.hs L(set_medium)
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+ mov val, v0.D[0]
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- .p2align 4
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/* Set 0..15 bytes. */
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-L(set_small):
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- add dstend, dstin, count
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- cmp count, 4
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- b.lo 2f
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- lsr off, count, 3
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- sub dstend2, dstend, off, lsl 2
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- str s0, [dstin]
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- str s0, [dstin, off, lsl 2]
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- str s0, [dstend2, -4]
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- str s0, [dstend, -4]
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+ tbz count, 3, 1f
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+ str val, [dstin]
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+ str val, [dstend, -8]
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+ ret
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+ nop
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+1: tbz count, 2, 2f
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+ str valw, [dstin]
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+ str valw, [dstend, -4]
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ret
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-
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- /* Set 0..3 bytes. */
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2: cbz count, 3f
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- lsr off, count, 1
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strb valw, [dstin]
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- strb valw, [dstin, off]
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- strb valw, [dstend, -1]
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+ tbz count, 1, 3f
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+ strh valw, [dstend, -2]
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3: ret
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+ /* Set 17..96 bytes. */
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+L(set_medium):
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+ str q0, [dstin]
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+ tbnz count, 6, L(set96)
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+ str q0, [dstend, -16]
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+ tbz count, 5, 1f
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+ str q0, [dstin, 16]
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+ str q0, [dstend, -32]
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+1: ret
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+
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.p2align 4
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-L(set_128):
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- bic dst, dstin, 15
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- cmp count, 128
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- b.hi L(set_long)
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- stp q0, q0, [dstin]
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+ /* Set 64..96 bytes. Write 64 bytes from the start and
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+ 32 bytes from the end. */
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+L(set96):
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+ str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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- stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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- .p2align 4
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+ .p2align 3
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+ nop
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L(set_long):
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+ and valw, valw, 255
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+ bic dst, dstin, 15
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str q0, [dstin]
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- str q0, [dst, 16]
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- tst valw, 255
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- b.ne L(no_zva)
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-#ifndef ZVA64_ONLY
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- mrs zva_val, dczid_el0
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- and zva_val, zva_val, 31
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- cmp zva_val, 4 /* ZVA size is 64 bytes. */
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- b.ne L(zva_128)
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-#endif
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- stp q0, q0, [dst, 32]
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- bic dst, dstin, 63
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- sub count, dstend, dst /* Count is now 64 too large. */
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- sub count, count, 64 + 64 /* Adjust count and bias for loop. */
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-
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- /* Write last bytes before ZVA loop. */
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- stp q0, q0, [dstend, -64]
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- stp q0, q0, [dstend, -32]
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-
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- .p2align 4
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-L(zva64_loop):
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- add dst, dst, 64
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- dc zva, dst
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+ cmp count, 256
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+ ccmp valw, 0, 0, cs
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+ b.eq L(try_zva)
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+L(no_zva):
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+ sub count, dstend, dst /* Count is 16 too large. */
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+ sub dst, dst, 16 /* Dst is biased by -32. */
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+ sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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+1: stp q0, q0, [dst, 32]
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+ stp q0, q0, [dst, 64]!
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+L(tail64):
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subs count, count, 64
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- b.hi L(zva64_loop)
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+ b.hi 1b
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+2: stp q0, q0, [dstend, -64]
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+ stp q0, q0, [dstend, -32]
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ret
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+L(try_zva):
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+#ifndef ZVA64_ONLY
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.p2align 3
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-L(no_zva):
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- sub count, dstend, dst /* Count is 32 too large. */
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- sub count, count, 64 + 32 /* Adjust count and bias for loop. */
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-L(no_zva_loop):
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+ mrs tmp1, dczid_el0
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+ tbnz tmp1w, 4, L(no_zva)
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+ and tmp1w, tmp1w, 15
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+ cmp tmp1w, 4 /* ZVA size is 64 bytes. */
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+ b.ne L(zva_128)
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+ nop
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+#endif
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+ /* Write the first and last 64 byte aligned block using stp rather
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+ than using DC ZVA. This is faster on some cores.
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+ */
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+ .p2align 4
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+L(zva_64):
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+ str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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+ bic dst, dst, 63
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stp q0, q0, [dst, 64]
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+ stp q0, q0, [dst, 96]
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+ sub count, dstend, dst /* Count is now 128 too large. */
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+ sub count, count, 128+64+64 /* Adjust count and bias for loop. */
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+ add dst, dst, 128
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+1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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- b.hi L(no_zva_loop)
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+ b.hi 1b
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+ stp q0, q0, [dst, 0]
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+ stp q0, q0, [dst, 32]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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#ifndef ZVA64_ONLY
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- .p2align 4
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+ .p2align 3
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L(zva_128):
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- cmp zva_val, 5 /* ZVA size is 128 bytes. */
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- b.ne L(no_zva)
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+ cmp tmp1w, 5 /* ZVA size is 128 bytes. */
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+ b.ne L(zva_other)
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+ str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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bic dst, dst, 127
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sub count, dstend, dst /* Count is now 128 too large. */
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- sub count, count, 128 + 128 /* Adjust count and bias for loop. */
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-1: add dst, dst, 128
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- dc zva, dst
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+ sub count, count, 128+128 /* Adjust count and bias for loop. */
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+ add dst, dst, 128
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+1: dc zva, dst
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+ add dst, dst, 128
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subs count, count, 128
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b.hi 1b
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stp q0, q0, [dstend, -128]
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@@ -158,6 +156,35 @@ L(zva_128):
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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+
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+L(zva_other):
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+ mov tmp2w, 4
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+ lsl zva_lenw, tmp2w, tmp1w
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+ add tmp1, zva_len, 64 /* Max alignment bytes written. */
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+ cmp count, tmp1
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+ blo L(no_zva)
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+
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+ sub tmp2, zva_len, 1
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+ add tmp1, dst, zva_len
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+ add dst, dst, 16
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+ subs count, tmp1, dst /* Actual alignment bytes to write. */
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+ bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
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+ beq 2f
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+1: stp q0, q0, [dst], 64
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+ stp q0, q0, [dst, -32]
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+ subs count, count, 64
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+ b.hi 1b
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+2: mov dst, tmp1
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+ sub count, dstend, tmp1 /* Remaining bytes to write. */
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+ subs count, count, zva_len
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+ b.lo 4f
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+3: dc zva, dst
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+ add dst, dst, zva_len
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+ subs count, count, zva_len
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+ b.hs 3b
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+4: add count, count, zva_len
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+ sub dst, dst, 32 /* Bias dst for tail loop. */
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+ b L(tail64)
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#endif
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END (MEMSET)
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@ -152,7 +152,7 @@ Version: %{glibcversion}
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# - It allows using the Release number without the %%dist tag in the dependency
|
||||
# generator to make the generated requires interchangeable between Rawhide
|
||||
# and ELN (.elnYY < .fcXX).
|
||||
%global baserelease 19
|
||||
%global baserelease 20
|
||||
Release: %{baserelease}%{?dist}
|
||||
|
||||
# Licenses:
|
||||
@ -342,6 +342,8 @@ Patch13: glibc-fedora-localedata-rh61908.patch
|
||||
Patch17: glibc-cs-path.patch
|
||||
Patch23: glibc-python3.patch
|
||||
Patch24: glibc-nolink-libc.patch
|
||||
Patch25: glibc-revert-1.patch
|
||||
Patch26: glibc-revert-2.patch
|
||||
|
||||
##############################################################################
|
||||
# Continued list of core "glibc" package information:
|
||||
@ -2358,6 +2360,9 @@ update_gconv_modules_cache ()
|
||||
%endif
|
||||
|
||||
%changelog
|
||||
* Thu Nov 21 2024 Florian Weimer <fweimer@redhat.com> - 2.40.9000-20
|
||||
- Revert aarch64 memset changes (cec3aef3241cec3aef32412779e) (#2327564)
|
||||
|
||||
* Wed Nov 20 2024 Florian Weimer <fweimer@redhat.com> - 2.40.9000-19
|
||||
- Auto-sync with upstream branch master,
|
||||
commit 47311cca31e685fa7bfe19bb8cef17d2d3d7fff9:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user