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commit 55efceabc6149e96134c10676adb2b1e79e0ae13
Author: Andreas Arnez <arnez@linux.vnet.ibm.com>
Date: Thu Jul 13 20:17:03 2017 +0200
S390: Add record/replay support for arch12 instructions
Support record/replay of the z/Architecture instructions that were
introduced with arch12.
gdb/ChangeLog:
* s390-linux-tdep.c (s390_process_record): Add support for
instructions new in arch12.
### a/gdb/ChangeLog
### b/gdb/ChangeLog
## -1,3 +1,8 @@
+2017-07-13 Andreas Arnez <arnez@linux.vnet.ibm.com>
+
+ * s390-linux-tdep.c (s390_process_record): Add support for
+ instructions new in arch12.
+
2017-07-11 John Baldwin <jhb@FreeBSD.org>
* amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use
--- a/gdb/s390-linux-tdep.c
+++ b/gdb/s390-linux-tdep.c
@@ -4992,6 +4992,8 @@ ex:
case 0xb9e9: /* SGRK - subtract */
case 0xb9ea: /* ALGRK - add logical */
case 0xb9eb: /* SLGRK - subtract logical */
+ case 0xb9ed: /* MSGRKC - multiply single 64x64 -> 64 */
+ case 0xb9fd: /* MSRKC - multiply single 32x32 -> 32 */
/* 64-bit gpr destination + flags */
if (s390_record_gpr_g (gdbarch, regcache, inib[6]))
return -1;
@@ -5019,7 +5021,7 @@ ex:
case 0xb914: /* LGFR - load */
case 0xb916: /* LLGFR - load logical */
case 0xb917: /* LLGTR - load logical thirty one bits */
- case 0xb91c: /* MSGFR - load */
+ case 0xb91c: /* MSGFR - multiply single 64<32 */
case 0xb946: /* BCTGR - branch on count */
case 0xb984: /* LLGCR - load logical character */
case 0xb985: /* LLGHR - load logical halfword */
@@ -5038,6 +5040,7 @@ ex:
case 0xb91d: /* DSGFR - divide single */
case 0xb986: /* MLGR - multiply logical */
case 0xb987: /* DLGR - divide logical */
+ case 0xb9ec: /* MGRK - multiply 64x64 -> 128 */
/* 64-bit gpr pair destination */
if (s390_record_gpr_g (gdbarch, regcache, inib[6]))
return -1;
@@ -5106,8 +5109,8 @@ ex:
/* 0xb922-0xb924 undefined */
/* 0xb925 privileged */
/* 0xb928 privileged */
- /* 0xb929 undefined */
+ case 0xb929: /* KMA - cipher message with authentication */
case 0xb92a: /* KMF - cipher message with cipher feedback [partial] */
case 0xb92b: /* KMO - cipher message with output feedback [partial] */
case 0xb92f: /* KMC - cipher message with chaining [partial] */
@@ -5170,6 +5173,15 @@ ex:
if (record_full_arch_list_add_reg (regcache, S390_R0_REGNUM + (inib[7] | 1)))
return -1;
}
+ if (tmp != 0 && insn[0] == 0xb929)
+ {
+ if (record_full_arch_list_add_reg (regcache,
+ S390_R0_REGNUM + inib[4]))
+ return -1;
+ if (record_full_arch_list_add_reg (regcache,
+ S390_R0_REGNUM + (inib[4] | 1)))
+ return -1;
+ }
if (record_full_arch_list_add_reg (regcache, S390_PSWM_REGNUM))
return -1;
break;
@@ -5571,10 +5583,11 @@ ex:
/* 0xb9e3 undefined */
/* 0xb9e5 undefined */
- /* 0xb9ec-0xb9f1 undefined */
+ /* 0xb9ee-0xb9f1 undefined */
/* 0xb9f3 undefined */
/* 0xb9f5 undefined */
- /* 0xb9fc-0xb9ff undefined */
+ /* 0xb9fc undefined */
+ /* 0xb9fe -0xb9ff undefined */
default:
goto UNKNOWN_OP;
@@ -5962,6 +5975,7 @@ ex:
break;
case 0xe3:
+ case 0xe6:
case 0xe7:
case 0xeb:
case 0xed:
@@ -6006,6 +6020,7 @@ ex:
case 0xe31c: /* MSGF - multiply single */
case 0xe32a: /* LZRG - load and zero rightmost byte */
case 0xe33a: /* LLZRGF - load logical and zero rightmost byte */
+ case 0xe33c: /* MGH - multiply halfword 64x16mem -> 64 */
case 0xe346: /* BCTG - branch on count */
case 0xe377: /* LGB - load byte */
case 0xe390: /* LLGC - load logical character */
@@ -6036,6 +6051,7 @@ ex:
case 0xe30d: /* DSG - divide single */
case 0xe31d: /* DSGF - divide single */
+ case 0xe384: /* MG - multiply 64x64mem -> 128 */
case 0xe386: /* MLG - multiply logical */
case 0xe387: /* DLG - divide logical */
case 0xe38f: /* LPQ - load pair from quadword */
@@ -6057,6 +6073,9 @@ ex:
/* 0xe310-0xe311 undefined */
case 0xe312: /* LT - load and test */
+ case 0xe338: /* AGH - add halfword to 64 bit value */
+ case 0xe339: /* SGH - subtract halfword from 64 bit value */
+ case 0xe353: /* MSC - multiply single 32x32mem -> 32 */
case 0xe354: /* NY - and */
case 0xe356: /* OY - or */
case 0xe357: /* XY - xor */
@@ -6066,13 +6085,14 @@ ex:
case 0xe35f: /* SLY - subtract logical */
case 0xe37a: /* AHY - add halfword */
case 0xe37b: /* SHY - subtract halfword */
+ case 0xe383: /* MSGC - multiply single 64x64mem -> 64 */
case 0xe398: /* ALC - add logical with carry */
case 0xe399: /* SLB - subtract logical with borrow */
case 0xe727: /* LCBB - load count to block bounduary */
case 0xeb81: /* ICMY - insert characters under mask */
case 0xebdc: /* SRAK - shift left single */
case 0xebdd: /* SLAK - shift left single */
- /* 32-bit gpr destination + flags */
+ /* 32/64-bit gpr destination + flags */
if (record_full_arch_list_add_reg (regcache, S390_R0_REGNUM + inib[2]))
return -1;
if (record_full_arch_list_add_reg (regcache, S390_PSWM_REGNUM))
@@ -6160,7 +6180,7 @@ ex:
case 0xe336: /* PFD - prefetch data */
break;
- /* 0xe337-0xe339 undefined */
+ /* 0xe337 undefined */
/* 0xe33c-0xe33d undefined */
case 0xe33e: /* STRV - store reversed */
@@ -6183,8 +6203,12 @@ ex:
break;
/* 0xe340-0xe345 undefined */
- /* 0xe347-0xe34f undefined */
- /* 0xe352-0xe353 undefined */
+
+ case 0xe347: /* BIC - branch indirect on condition */
+ break;
+
+ /* 0xe348-0xe34f undefined */
+ /* 0xe352 undefined */
case 0xe35c: /* MFY - multiply */
case 0xe396: /* ML - multiply logical */
@@ -6216,11 +6240,12 @@ ex:
break;
/* 0xe37d-0xe37f undefined */
- /* 0xe383-0xe384 undefined */
case 0xe385: /* LGAT - load and trap */
case 0xe39c: /* LLGTAT - load logical thirty one bits and trap */
case 0xe39d: /* LLGFAT - load logical and trap */
+ case 0xe650: /* VCVB - vector convert to binary 32 bit*/
+ case 0xe652: /* VCVBG - vector convert to binary 64 bit*/
case 0xe721: /* VLGV - vector load gr from vr element */
/* 64-bit gpr destination + fpc for possible DXC write */
if (s390_record_gpr_g (gdbarch, regcache, inib[2]))
@@ -6271,6 +6296,10 @@ ex:
/* 0xe3ce undefined */
/* 0xe3d0-0xe3ff undefined */
+ case 0xe634: /* VPKZ - vector pack zoned */
+ case 0xe635: /* VLRL - vector load rightmost with immed. length */
+ case 0xe637: /* VLRLR - vector load rightmost with length */
+ case 0xe649: /* VLIP - vector load immediate decimal */
case 0xe700: /* VLEB - vector load element */
case 0xe701: /* VLEH - vector load element */
case 0xe702: /* VLEG - vector load element */
@@ -6311,7 +6340,10 @@ ex:
case 0xe769: /* VNC - vector and with complement */
case 0xe76a: /* VO - vector or */
case 0xe76b: /* VNO - vector nor */
+ case 0xe76c: /* VNX - vector not exclusive or */
case 0xe76d: /* VX - vector xor */
+ case 0xe76e: /* VNN - vector nand */
+ case 0xe76f: /* VOC - vector or with complement */
case 0xe770: /* VESLV - vector element shift left */
case 0xe772: /* VERIM - vector element rotate and insert under mask */
case 0xe773: /* VERLLV - vector element rotate left logical */
@@ -6325,11 +6357,14 @@ ex:
case 0xe77e: /* VSRA - vector shift right arithmetic */
case 0xe77f: /* VSRAB - vector shift right arithmetic by byte */
case 0xe784: /* VPDI - vector permute doubleword immediate */
+ case 0xe785: /* VBPERM - vector bit permute */
case 0xe78c: /* VPERM - vector permute */
case 0xe78d: /* VSEL - vector select */
case 0xe78e: /* VFMS - vector fp multiply and subtract */
case 0xe78f: /* VFMA - vector fp multiply and add */
case 0xe794: /* VPK - vector pack */
+ case 0xe79e: /* VFNMS - vector fp negative multiply and subtract */
+ case 0xe79f: /* VFNMA - vector fp negative multiply and add */
case 0xe7a1: /* VMLH - vector multiply logical high */
case 0xe7a2: /* VML - vector multiply low */
case 0xe7a3: /* VMH - vector multiply high */
@@ -6345,6 +6380,7 @@ ex:
case 0xe7ae: /* VMAE - vector multiply and add even */
case 0xe7af: /* VMAO - vector multiply and add odd */
case 0xe7b4: /* VGFM - vector Galois field multiply sum */
+ case 0xe7b8: /* VMSL - vector multiply sum logical */
case 0xe7b9: /* VACCC - vector add with carry compute carry */
case 0xe7bb: /* VAC - vector add with carry */
case 0xe7bc: /* VGFMA - vector Galois field multiply sum and accumulate */
@@ -6354,8 +6390,8 @@ ex:
case 0xe7c1: /* VCDLG - vector convert from logical 64-bit */
case 0xe7c2: /* VCGD - vector convert to fixed 64-bit */
case 0xe7c3: /* VCDG - vector convert from fixed 64-bit */
- case 0xe7c4: /* VLDE - vector fp load lengthened */
- case 0xe7c5: /* VLED - vector fp load rounded */
+ case 0xe7c4: /* VLDE/VFLL - vector fp load lengthened */
+ case 0xe7c5: /* VLED/VFLR - vector fp load rounded */
case 0xe7c7: /* VFI - vector load fp integer */
case 0xe7cc: /* VFPSO - vector fp perform sign operation */
case 0xe7ce: /* VFSQ - vector fp square root */
@@ -6369,6 +6405,8 @@ ex:
case 0xe7e3: /* VFA - vector fp add */
case 0xe7e5: /* VFD - vector fp divide */
case 0xe7e7: /* VFM - vector fp multiply */
+ case 0xe7ee: /* VFMIN - vector fp minimum */
+ case 0xe7ef: /* VFMAX - vector fp maximum */
case 0xe7f0: /* VAVGL - vector average logical */
case 0xe7f1: /* VACC - vector add and compute carry */
case 0xe7f2: /* VAVG - vector average */
@@ -6386,6 +6424,14 @@ ex:
return -1;
break;
+ case 0xe63d: /* VSTRL - vector store rightmost with immed. length */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, 0, insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, inib[3] + 1))
+ return -1;
+ if (record_full_arch_list_add_reg (regcache, S390_FPC_REGNUM))
+ return -1;
+ break;
+
case 0xe708: /* VSTEB - vector store element */
oaddr = s390_record_calc_disp (gdbarch, regcache, inib[3], insn[1], 0);
if (record_full_arch_list_add_mem (oaddr, 1))
@@ -6480,13 +6526,22 @@ ex:
return -1;
break;
+ case 0xe63c: /* VUPKZ - vector unpack zoned */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, 0, insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, (ibyte[1] + 1) & 31))
+ return -1;
+ if (record_full_arch_list_add_reg (regcache, S390_PSWM_REGNUM))
+ return -1;
+ break;
+
+ case 0xe63f: /* VSTRLR - vector store rightmost with length */
case 0xe73f: /* VSTL - vector store with length */
oaddr = s390_record_calc_disp (gdbarch, regcache, 0, insn[1], 0);
regcache_raw_read_unsigned (regcache, S390_R0_REGNUM + inib[3], &tmp);
tmp &= 0xffffffffu;
- if (tmp > 16)
- tmp = 16;
- if (record_full_arch_list_add_mem (oaddr, tmp))
+ if (tmp > 15)
+ tmp = 15;
+ if (record_full_arch_list_add_mem (oaddr, tmp + 1))
return -1;
if (record_full_arch_list_add_reg (regcache, S390_FPC_REGNUM))
return -1;
@@ -6494,6 +6549,17 @@ ex:
/* 0xe747-0xe749 undefined */
+ case 0xe658: /* VCVD - vector convert to decimal 32 bit */
+ case 0xe659: /* VSRP - vector shift and round decimal */
+ case 0xe65a: /* VCVDG - vector convert to decimal 64 bit*/
+ case 0xe65b: /* VPSOP - vector perform sign operation decimal */
+ case 0xe671: /* VAP - vector add decimal */
+ case 0xe673: /* VSP - vector subtract decimal */
+ case 0xe678: /* VMP - vector multiply decimal */
+ case 0xe679: /* VMSP - vector multiply decimal */
+ case 0xe67a: /* VDP - vector divide decimal */
+ case 0xe67b: /* VRP - vector remainder decimal */
+ case 0xe67e: /* VSDP - vector shift and divide decimal */
case 0xe74a: /* VFTCI - vector fp test data class immediate */
case 0xe75c: /* VISTR - vector isolate string */
case 0xe780: /* VFEE - vector find element equal */
@@ -6504,7 +6570,7 @@ ex:
case 0xe797: /* VPKS - vector pack saturate */
case 0xe7e8: /* VFCE - vector fp compare equal */
case 0xe7ea: /* VFCHE - vector fp compare high or equal */
- case 0xe7eb: /* VFCE - vector fp compare high */
+ case 0xe7eb: /* VFCH - vector fp compare high */
case 0xe7f8: /* VCEQ - vector compare equal */
case 0xe7f9: /* VCHL - vector compare high logical */
case 0xe7fb: /* VCH - vector compare high */
@@ -6517,6 +6583,14 @@ ex:
return -1;
break;
+ case 0xe65f: /* VTP - vector test decimal */
+ /* flags + FPC */
+ if (record_full_arch_list_add_reg (regcache, S390_PSWM_REGNUM))
+ return -1;
+ if (record_full_arch_list_add_reg (regcache, S390_FPC_REGNUM))
+ return -1;
+ break;
+
/* 0xe74b-0xe74c undefined */
/* 0xe74e-0xe74f undefined */
/* 0xe751 undefined */
@@ -6524,26 +6598,26 @@ ex:
/* 0xe757-0xe75b undefined */
/* 0xe75d-0xe75e undefined */
/* 0xe763 undefined */
- /* 0xe76c undefined */
- /* 0xe76e-0xe76f undefined */
/* 0xe771 undefined */
/* 0xe776 undefined */
/* 0xe779 undefined */
/* 0xe77b undefined */
/* 0xe783 undefined */
- /* 0xe785-0xe789 undefined */
+ /* 0xe786-0xe789 undefined */
/* 0xe78b undefined */
/* 0xe790-0xe793 undefined */
/* 0xe796 undefined */
- /* 0xe798-0xe7a0 undefined */
- /* 0xe7a8 undefined */
+ /* 0xe798-0xe79d undefined */
+ /* 0xe7a0 undefined */
+ /* 0xe7a8 undefined */
/* 0xe7b0-0xe7b3 undefined */
- /* 0xe7b5-0xe7b8 undefined */
+ /* 0xe7b5-0xe7b7 undefined */
/* 0xe7ba undefined */
/* 0xe7be undefined */
/* 0xe7c6 undefined */
/* 0xe7c8-0xe7c9 undefined */
+ case 0xe677: /* VCP - vector compare decimal */
case 0xe7ca: /* WFK - vector fp compare and signal scalar */
case 0xe7cb: /* WFC - vector fp compare scalar */
case 0xe7d8: /* VTM - vector test under mask */
@@ -6568,7 +6642,7 @@ ex:
/* 0xe7e4 undefined */
/* 0xe7e6 undefined */
/* 0xe7e9 undefined */
- /* 0xe7ec-0xe7ef undefined */
+ /* 0xe7ec-0xe7ed undefined */
/* 0xe7f4 undefined */
/* 0xe7f6 undefined */
/* 0xe7fa undefined */
@@ -7048,8 +7122,6 @@ ex:
}
break;
- /* 0xe6 undefined */
-
case 0xec:
/* RIE/RIS/RRS-format instruction */
switch (ibyte[0] << 8 | ibyte[5])
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