Update from FSF GDB 7.12 stable branch to snapshot: gdb-7.12.0.20170111

This commit is contained in:
Jan Kratochvil 2017-01-11 18:11:21 +01:00
parent 6022fd9542
commit 718f2d69b3
4 changed files with 7 additions and 146 deletions

2
.gitignore vendored
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@ -1,3 +1,3 @@
/gdb-libstdc++-v3-python-6.1.1-20160817.tar.xz
/v1.5.tar.gz
/gdb-7.12.tar.xz
/gdb-7.12.0.20170111.tar.xz

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@ -1,138 +0,0 @@
http://sourceware.org/ml/gdb-patches/2016-10/msg00287.html
Subject: Re: aarch64 regression: gdb.cp/nextoverthrow.exp [Re: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue]
Jan Kratochvil <jan.kratochvil@redhat.com> writes:
>> Could you open a ticket in bugzilla for this error? I am testing a patch.
>
> https://sourceware.org/bugzilla/show_bug.cgi?id=20682
Thanks, here is the patch...
--
Yao (齐尧)
>From 5794d10bcda63da8fc47d0a76c29669af83ed48b Mon Sep 17 00:00:00 2001
From: Yao Qi <yao.qi@linaro.org>
Date: Tue, 11 Oct 2016 12:12:46 +0100
Subject: [PATCH] [AArch64] Track FP registers in prologue analyzer
We don't track FP registers in aarch64 prologue analyzer, so this causes
an internal error when FP registers are saved by "stp" instruction in
prologue (stp d8, d9, [sp,#128]),
tbreak _Unwind_RaiseException^M
aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
A problem internal to GDB has been detected,
This patch teaches GDB to track FP registers (D registers) in prologue
analyzer.
gdb:
2016-10-12 Yao Qi <yao.qi@linaro.org>
PR tdep/20682
* aarch64-tdep.c: Replace 32 with AARCH64_D_REGISTER_COUNT.
(aarch64_analyze_prologue): Extend array 'regs' for D registers.
Assert that operand 0 and 1 can be X or D registers. Update
register number for D registers. Update registers in frame
cache.
* aarch64-tdep.h (AARCH64_D_REGISTER_COUNT): New macro.
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 16dd365..be72785 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -68,7 +68,7 @@
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
-#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
+#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
@@ -206,11 +206,12 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
- pv_t regs[AARCH64_X_REGISTER_COUNT];
+ /* Track X registers and D registers in prologue. */
+ pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
struct pv_area *stack;
struct cleanup *back_to;
- for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
+ for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
regs[i] = pv_register (i, 0);
stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
back_to = make_cleanup_free_pv_area (stack);
@@ -328,13 +329,15 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
&& strcmp ("stp", inst.opcode->name) == 0)
{
/* STP with addressing mode Pre-indexed and Base register. */
- unsigned rt1 = inst.operands[0].reg.regno;
- unsigned rt2 = inst.operands[1].reg.regno;
+ unsigned rt1;
+ unsigned rt2;
unsigned rn = inst.operands[2].addr.base_regno;
int32_t imm = inst.operands[2].addr.offset.imm;
- gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
- gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2);
+ gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
+ || inst.operands[0].type == AARCH64_OPND_Ft);
+ gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
+ || inst.operands[1].type == AARCH64_OPND_Ft2);
gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
gdb_assert (!inst.operands[2].addr.offset.is_reg);
@@ -349,6 +352,17 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
pv_add_constant (regs[rn], imm + 8)))
break;
+ rt1 = inst.operands[0].reg.regno;
+ rt2 = inst.operands[1].reg.regno;
+ if (inst.operands[0].type == AARCH64_OPND_Ft)
+ {
+ /* Only bottom 64-bit of each V register (D register) need
+ to be preserved. */
+ gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
+ rt1 += AARCH64_X_REGISTER_COUNT;
+ rt2 += AARCH64_X_REGISTER_COUNT;
+ }
+
pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
regs[rt1]);
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
@@ -408,6 +422,16 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
cache->saved_regs[i].addr = offset;
}
+ for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
+ {
+ int regnum = gdbarch_num_regs (gdbarch);
+ CORE_ADDR offset;
+
+ if (pv_area_find_reg (stack, gdbarch, i + AARCH64_X_REGISTER_COUNT,
+ &offset))
+ cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
+ }
+
do_cleanups (back_to);
return start;
}
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index a95b613..6252820 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -68,6 +68,8 @@ enum aarch64_regnum
/* Total number of general (X) registers. */
#define AARCH64_X_REGISTER_COUNT 32
+/* Total number of D registers. */
+#define AARCH64_D_REGISTER_COUNT 32
/* The maximum number of modified instructions generated for one
single-stepped instruction. */

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@ -21,12 +21,12 @@ Name: %{?scl_prefix}gdb
%global snapsrc 20160801
# See timestamp of source gnulib installed into gdb/gnulib/ .
%global snapgnulib 20150822
%global tarname gdb-%{version}
%global tarname gdb-7.12.0.20170111
Version: 7.12
# The release always contains a leading reserved number, start it at 1.
# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
Release: 35%{?dist}
Release: 36%{?dist}
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and BSD and Public Domain and GFDL
Group: Development/Debuggers
@ -635,9 +635,6 @@ Patch1144: gdb-bison-old.patch
Patch1145: gdb-testsuite-casts.patch
Patch1146: gdb-testsuite-m-static.patch
# [aarch64] Fix gdb.cp/nextoverthrow.exp regression (Yao Qi).
Patch1148: gdb-aarch64-nextoverthrow.patch
# Fix TLS (such as 'errno') regression.
Patch1149: gdb-tls-1of2.patch
Patch1150: gdb-tls-2of2.patch
@ -1018,7 +1015,6 @@ done
%patch1144 -p1
%patch1145 -p1
%patch1146 -p1
%patch1148 -p1
%patch1149 -p1
%patch1150 -p1
%patch1151 -p1
@ -1583,6 +1579,9 @@ then
fi
%changelog
* Wed Jan 11 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.12-36.fc25
- Update from FSF GDB 7.12 stable branch to snapshot: gdb-7.12.0.20170111
* Sun Jan 8 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.12-35.fc25
- Fix Python backtraces for 32-bit inferiors (Tom Tromey, RH BZ 1411094).

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@ -1,3 +1,3 @@
SHA512 (gdb-libstdc++-v3-python-6.1.1-20160817.tar.xz) = 2f3030ec6cf379dbfbdb4e515cc47dcb47f25327c046759ad8f117e290e0300eed58969a432552203966cd6b02e5279c95309a4b2228ed98d8cd63f0a4f5cfc4
SHA512 (v1.5.tar.gz) = ea3e76291d5b077d5b42061898a1f70af6cbdbccb7d05c59904f322ca1c03f7596cac6a966b80b12d2c2d86212f17d6bde02b1daf92be62e49abcb234e2bacbd
SHA512 (gdb-7.12.tar.xz) = f610338b3a24dfb387c295431d806a0c1375e8ce51b8dd8bbfd2efc4612d0c0ed40ad4393508afca0071eca70688f62bc4f199da5e75ad16f64d91c3bc046033
SHA512 (gdb-7.12.0.20170111.tar.xz) = 8673b3614331306633939f3a744185e60405aa5382a06cc68ff189518d7b4d6adc761b63456d9a566a88d0a44174457882a603381d03175a353a65aa60d6db55