208 lines
6.0 KiB
Diff
208 lines
6.0 KiB
Diff
2010-06-24 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/44492
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* recog.h (struct recog_data): Add is_asm field.
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* recog.c (asm_operand_ok, constrain_operands): If neither < nor > is
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present in constraints of inline-asm operand and memory operand
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contains {PRE,POST}_{INC,DEC,MODIFY}, return 0.
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(extract_insn): Initialize recog_data.is_asm.
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* doc/md.texi (Constraints): Document operand side-effect rules.
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* g++.dg/torture/pr44492.C: New test.
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--- gcc/doc/md.texi (revision 161327)
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+++ gcc/doc/md.texi (revision 161328)
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@@ -1052,6 +1052,10 @@ an operand may be in a register, and whi
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operand can be a memory reference, and which kinds of address; whether the
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operand may be an immediate constant, and which possible values it may
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have. Constraints can also require two operands to match.
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+Side-effects aren't allowed in operands of inline @code{asm}, unless
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+@samp{<} or @samp{>} constraints are used, because there is no guarantee
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+that the side-effects will happen exactly once in an instruction that can update
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+the addressing register.
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@ifset INTERNALS
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@menu
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@@ -1129,12 +1133,21 @@ would fit the @samp{m} constraint but no
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@cindex @samp{<} in constraint
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@item @samp{<}
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A memory operand with autodecrement addressing (either predecrement or
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-postdecrement) is allowed.
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+postdecrement) is allowed. In inline @code{asm} this constraint is only
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+allowed if the operand is used exactly once in an instruction that can
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+handle the side-effects. Not using an operand with @samp{<} in constraint
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+string in the inline @code{asm} pattern at all or using it in multiple
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+instructions isn't valid, because the side-effects wouldn't be performed
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+or would be performed more than once. Furthermore, on some targets
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+the operand with @samp{<} in constraint string must be accompanied by
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+special instruction suffixes like @code{%U0} instruction suffix on PowerPC
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+or @code{%P0} on IA-64.
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@cindex @samp{>} in constraint
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@item @samp{>}
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A memory operand with autoincrement addressing (either preincrement or
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-postincrement) is allowed.
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+postincrement) is allowed. In inline @code{asm} the same restrictions
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+as for @samp{<} apply.
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@cindex @samp{r} in constraint
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@cindex registers in constraints
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--- gcc/recog.c (revision 161327)
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+++ gcc/recog.c (revision 161328)
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@@ -1601,6 +1601,9 @@ int
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asm_operand_ok (rtx op, const char *constraint, const char **constraints)
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{
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int result = 0;
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+#ifdef AUTO_INC_DEC
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+ bool incdec_ok = false;
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+#endif
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/* Use constrain_operands after reload. */
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gcc_assert (!reload_completed);
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@@ -1608,7 +1611,7 @@ asm_operand_ok (rtx op, const char *cons
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/* Empty constraint string is the same as "X,...,X", i.e. X for as
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many alternatives as required to match the other operands. */
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if (*constraint == '\0')
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- return 1;
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+ result = 1;
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while (*constraint)
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{
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@@ -1685,6 +1688,9 @@ asm_operand_ok (rtx op, const char *cons
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|| GET_CODE (XEXP (op, 0)) == PRE_DEC
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|| GET_CODE (XEXP (op, 0)) == POST_DEC))
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result = 1;
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+#ifdef AUTO_INC_DEC
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+ incdec_ok = true;
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+#endif
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break;
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case '>':
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@@ -1693,6 +1699,9 @@ asm_operand_ok (rtx op, const char *cons
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|| GET_CODE (XEXP (op, 0)) == PRE_INC
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|| GET_CODE (XEXP (op, 0)) == POST_INC))
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result = 1;
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+#ifdef AUTO_INC_DEC
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+ incdec_ok = true;
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+#endif
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break;
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case 'E':
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@@ -1814,6 +1823,23 @@ asm_operand_ok (rtx op, const char *cons
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return 0;
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}
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+#ifdef AUTO_INC_DEC
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+ /* For operands without < or > constraints reject side-effects. */
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+ if (!incdec_ok && result && MEM_P (op))
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+ switch (GET_CODE (XEXP (op, 0)))
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+ {
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+ case PRE_INC:
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+ case POST_INC:
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+ case PRE_DEC:
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+ case POST_DEC:
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+ case PRE_MODIFY:
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+ case POST_MODIFY:
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+ return 0;
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+ default:
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+ break;
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+ }
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+#endif
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+
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return result;
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}
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@@ -2039,6 +2065,7 @@ extract_insn (rtx insn)
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recog_data.n_operands = 0;
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recog_data.n_alternatives = 0;
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recog_data.n_dups = 0;
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+ recog_data.is_asm = false;
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switch (GET_CODE (body))
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{
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@@ -2085,6 +2112,7 @@ extract_insn (rtx insn)
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while (*p)
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recog_data.n_alternatives += (*p++ == ',');
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}
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+ recog_data.is_asm = true;
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break;
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}
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fatal_insn_not_found (insn);
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@@ -2699,6 +2727,30 @@ constrain_operands (int strict)
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= recog_data.operand[funny_match[funny_match_index].this_op];
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}
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+#ifdef AUTO_INC_DEC
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+ /* For operands without < or > constraints reject side-effects. */
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+ if (recog_data.is_asm)
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+ {
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+ for (opno = 0; opno < recog_data.n_operands; opno++)
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+ if (MEM_P (recog_data.operand[opno]))
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+ switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
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+ {
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+ case PRE_INC:
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+ case POST_INC:
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+ case PRE_DEC:
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+ case POST_DEC:
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+ case PRE_MODIFY:
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+ case POST_MODIFY:
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+ if (strchr (recog_data.constraints[opno], '<') == NULL
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+ || strchr (recog_data.constraints[opno], '>')
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+ == NULL)
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+ return 0;
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+#endif
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return 1;
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}
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}
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--- gcc/recog.h (revision 161327)
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+++ gcc/recog.h (revision 161328)
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@@ -230,6 +230,9 @@ struct recog_data
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/* The number of alternatives in the constraints for the insn. */
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char n_alternatives;
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+ /* True if insn is ASM_OPERANDS. */
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+ bool is_asm;
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+
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/* Specifies whether an insn alternative is enabled using the
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`enabled' attribute in the insn pattern definition. For back
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ends not using the `enabled' attribute the array fields are
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--- gcc/testsuite/g++.dg/torture/pr44492.C (revision 0)
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+++ gcc/testsuite/g++.dg/torture/pr44492.C (revision 161328)
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@@ -0,0 +1,31 @@
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+// PR middle-end/44492
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+// { dg-do run }
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+
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+struct T { unsigned long p; };
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+struct S { T a, b, c; unsigned d; };
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+
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+__attribute__((noinline))
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+void
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+bar (const T &x, const T &y)
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+{
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+ if (x.p != 0x2348 || y.p != 0x2346)
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+ __builtin_abort ();
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+}
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+
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+__attribute__((noinline))
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+void
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+foo (S &s, T e)
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+{
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+ unsigned long a = e.p;
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+ unsigned long b = s.b.p;
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+ __asm__ volatile ("" : : "rm" (a), "rm" (b));
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+ bar (e, s.b);
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+}
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+
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+int
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+main ()
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+{
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+ S s = { { 0x2345 }, { 0x2346 }, { 0x2347 }, 6 };
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+ T t = { 0x2348 };
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+ foo (s, t);
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+}
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