118 lines
4.1 KiB
Diff
118 lines
4.1 KiB
Diff
From cb398a612ed5f5110adaaaea338447b6e933067d Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Wed, 5 Apr 2023 09:48:06 -0700
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Subject: [PATCH] RISC-V: Eliminate AMO op fences
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Atomic operations with the appropriate bits set already enfore release
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semantics. Remove unnecessary release fences from atomic ops.
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This change brings AMO ops in line with table A.6 of the ISA manual.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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gcc/ChangeLog:
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* config/riscv/riscv.cc
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(riscv_memmodel_needs_amo_release): Change function name.
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(riscv_print_operand): Remove unneeded %F case.
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* config/riscv/sync.md: Remove unneeded fences.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/riscv.cc | 16 +++++-----------
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gcc/config/riscv/sync.md | 12 ++++++------
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2 files changed, 11 insertions(+), 17 deletions(-)
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
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index df55c427b1b3..951f6b5cf42d 100644
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--- a/gcc/config/riscv/riscv.cc
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+++ b/gcc/config/riscv/riscv.cc
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@@ -4307,11 +4307,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
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}
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}
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-/* Return true if a FENCE should be emitted to before a memory access to
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- implement the release portion of memory model MODEL. */
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+/* Return true if the .RL suffix should be added to an AMO to implement the
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+ release portion of memory model MODEL. */
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static bool
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-riscv_memmodel_needs_release_fence (enum memmodel model)
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+riscv_memmodel_needs_amo_release (enum memmodel model)
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{
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switch (model)
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{
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@@ -4337,7 +4337,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
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'R' Print the low-part relocation associated with OP.
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'C' Print the integer branch condition for comparison OP.
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'A' Print the atomic operation suffix for memory model OP.
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- 'F' Print a FENCE if the memory model requires a release.
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'z' Print x0 if OP is zero, otherwise print OP normally.
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'i' Print i if the operand is not a register.
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'S' Print shift-index of single-bit mask OP.
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@@ -4499,19 +4498,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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case 'A':
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if (riscv_memmodel_needs_amo_acquire (model)
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- && riscv_memmodel_needs_release_fence (model))
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+ && riscv_memmodel_needs_amo_release (model))
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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- else if (riscv_memmodel_needs_release_fence (model))
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+ else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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break;
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- case 'F':
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- if (riscv_memmodel_needs_release_fence (model))
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- fputs ("fence iorw,ow; ", file);
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- break;
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-
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case 'i':
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if (code != REG)
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fputs ("i", file);
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diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
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index 1acb78a9ae4c..9a3b57bd09fd 100644
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--- a/gcc/config/riscv/sync.md
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+++ b/gcc/config/riscv/sync.md
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@@ -91,9 +91,9 @@
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))]
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"TARGET_ATOMIC"
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- "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
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+ "amo<insn>.<amo>%A2\tzero,%z1,%0"
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[(set_attr "type" "atomic")
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- (set (attr "length") (const_int 8))])
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+ (set (attr "length") (const_int 4))])
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(define_insn "atomic_fetch_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&r")
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@@ -105,9 +105,9 @@
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))]
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"TARGET_ATOMIC"
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- "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
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+ "amo<insn>.<amo>%A3\t%0,%z2,%1"
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[(set_attr "type" "atomic")
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- (set (attr "length") (const_int 8))])
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+ (set (attr "length") (const_int 4))])
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(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
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[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
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@@ -247,9 +247,9 @@
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(set (match_dup 1)
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(match_operand:GPR 2 "register_operand" "0"))]
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"TARGET_ATOMIC"
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- "%F3amoswap.<amo>%A3 %0,%z2,%1"
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+ "amoswap.<amo>%A3\t%0,%z2,%1"
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[(set_attr "type" "atomic")
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- (set (attr "length") (const_int 8))])
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+ (set (attr "length") (const_int 4))])
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(define_expand "atomic_exchange<mode>"
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[(match_operand:SHORT 0 "register_operand") ;; old value at mem
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--
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2.39.3
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