138 lines
4.3 KiB
Diff
138 lines
4.3 KiB
Diff
From 9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0 Mon Sep 17 00:00:00 2001
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From: Li Xu <xuli1@eswincomputing.com>
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Date: Wed, 10 May 2023 04:02:13 +0000
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Subject: [PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
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instructions satisfying REG_P(operand[1]) in -O0.
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This issue happens is because the operand1 of scalar move can be
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REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
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not insert the vsetvl instruction correctly, and the compiler crashes.
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Consider this following case:
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int16_t foo1 (void *base, size_t vl)
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{
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int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
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return maxVal;
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}
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Before this patch:
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bug.c:15:1: internal compiler error: Segmentation fault
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15 | }
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| ^
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0x145d723 crash_signal
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../.././riscv-gcc/gcc/toplev.cc:314
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0x22929dd const_csr_operand(rtx_def*, machine_mode)
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../.././riscv-gcc/gcc/config/riscv/predicates.md:44
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0x2292a21 csr_operand(rtx_def*, machine_mode)
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../.././riscv-gcc/gcc/config/riscv/predicates.md:46
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0x23dfbb0 recog_356
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../.././riscv-gcc/gcc/config/riscv/iterators.md:72
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0x23efecd recog(rtx_def*, rtx_insn*, int*)
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../.././riscv-gcc/gcc/config/riscv/iterators.md:89
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0xdddc15 recog_memoized(rtx_insn*)
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../.././riscv-gcc/gcc/recog.h:273
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After this patch:
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vsetivli zero,0,e16,m1,ta,ma
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vmv.x.s a5,v1
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gcc/ChangeLog:
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* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
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intruction replace null avl with (const_int 0).
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gcc/testsuite/ChangeLog:
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* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
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* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
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---
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gcc/config/riscv/riscv-vsetvl.cc | 5 +++
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.../riscv/rvv/base/scalar_move-10.c | 31 +++++++++++++++++++
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.../riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++
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3 files changed, 56 insertions(+)
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
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index bd45cb97e63b..0cf4bc818e2a 100644
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--- a/gcc/config/riscv/riscv-vsetvl.cc
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+++ b/gcc/config/riscv/riscv-vsetvl.cc
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@@ -618,6 +618,11 @@ static rtx
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gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info &info, rtx vl)
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{
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rtx avl = info.get_avl ();
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+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
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+ set the value of avl to (const_int 0) so that VSETVL PASS will
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+ insert vsetvl correctly.*/
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+ if (info.has_avl_no_reg ())
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+ avl = GEN_INT (0);
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rtx sew = gen_int_mode (info.get_sew (), Pmode);
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rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
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rtx ta = gen_int_mode (info.get_ta (), Pmode);
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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new file mode 100644
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index 000000000000..9760d77fb22b
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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@@ -0,0 +1,31 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
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+/* { dg-final { check-function-bodies "**" "" } } */
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+
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+#include "riscv_vector.h"
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+
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+/*
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+** foo1:
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+** ...
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+** vsetivli\tzero,0,e16,m1,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+int16_t foo1 (void *base, size_t vl)
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+{
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+ int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
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+ return maxVal;
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+}
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+
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+/*
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+** foo2:
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+** ...
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+** vsetivli\tzero,0,e32,m1,t[au],m[au]
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+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+float foo2 (void *base, size_t vl)
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+{
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+ float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base, vl));
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+ return maxVal;
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+}
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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new file mode 100644
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index 000000000000..8036acd0a529
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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@@ -0,0 +1,20 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
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+/* { dg-final { check-function-bodies "**" "" } } */
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+
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+#include "riscv_vector.h"
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+
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+/*
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+** foo:
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+** ...
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+** vsetivli\tzero,0,e64,m4,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** vsetivli\tzero,0,e64,m4,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+int16_t foo (void *base, size_t vl)
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+{
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+ int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base, vl));
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+ return maxVal;
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+}
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--
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2.39.3
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