88 lines
2.7 KiB
Diff
88 lines
2.7 KiB
Diff
From 74abe200bc9b06e10f0f3cad74f11da4fae90cd3 Mon Sep 17 00:00:00 2001
|
|
From: Patrick O'Neill <patrick@rivosinc.com>
|
|
Date: Wed, 5 Apr 2023 09:56:33 -0700
|
|
Subject: [PATCH] RISC-V: Strengthen atomic stores
|
|
|
|
This change makes atomic stores strictly stronger than table A.6 of the
|
|
ISA manual. This mapping makes the overall patchset compatible with
|
|
table A.7 as well.
|
|
|
|
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
|
|
|
|
PR target/89835
|
|
|
|
gcc/ChangeLog:
|
|
|
|
* config/riscv/sync.md (atomic_store<mode>): Use simple store
|
|
instruction in combination with fence(s).
|
|
|
|
gcc/testsuite/ChangeLog:
|
|
|
|
* gcc.target/riscv/pr89835.c: New test.
|
|
|
|
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
|
|
---
|
|
gcc/config/riscv/sync.md | 21 ++++++++++++++++++---
|
|
gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++
|
|
2 files changed, 27 insertions(+), 3 deletions(-)
|
|
create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c
|
|
|
|
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
|
|
index 5620d6ffa587..1acb78a9ae4c 100644
|
|
--- a/gcc/config/riscv/sync.md
|
|
+++ b/gcc/config/riscv/sync.md
|
|
@@ -56,7 +56,9 @@
|
|
|
|
;; Atomic memory operations.
|
|
|
|
-;; Implement atomic stores with amoswap. Fall back to fences for atomic loads.
|
|
+;; Implement atomic stores with conservative fences. Fall back to fences for
|
|
+;; atomic loads.
|
|
+;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7.
|
|
(define_insn "atomic_store<mode>"
|
|
[(set (match_operand:GPR 0 "memory_operand" "=A")
|
|
(unspec_volatile:GPR
|
|
@@ -64,9 +66,22 @@
|
|
(match_operand:SI 2 "const_int_operand")] ;; model
|
|
UNSPEC_ATOMIC_STORE))]
|
|
"TARGET_ATOMIC"
|
|
- "%F2amoswap.<amo>%A2 zero,%z1,%0"
|
|
+ {
|
|
+ enum memmodel model = (enum memmodel) INTVAL (operands[2]);
|
|
+ model = memmodel_base (model);
|
|
+
|
|
+ if (model == MEMMODEL_SEQ_CST)
|
|
+ return "fence\trw,w\;"
|
|
+ "s<amo>\t%z1,%0\;"
|
|
+ "fence\trw,rw";
|
|
+ if (model == MEMMODEL_RELEASE)
|
|
+ return "fence\trw,w\;"
|
|
+ "s<amo>\t%z1,%0";
|
|
+ else
|
|
+ return "s<amo>\t%z1,%0";
|
|
+ }
|
|
[(set_attr "type" "atomic")
|
|
- (set (attr "length") (const_int 8))])
|
|
+ (set (attr "length") (const_int 12))])
|
|
|
|
(define_insn "atomic_<atomic_optab><mode>"
|
|
[(set (match_operand:GPR 0 "memory_operand" "+A")
|
|
diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c
|
|
new file mode 100644
|
|
index 000000000000..ab190e11b608
|
|
--- /dev/null
|
|
+++ b/gcc/testsuite/gcc.target/riscv/pr89835.c
|
|
@@ -0,0 +1,9 @@
|
|
+/* { dg-do compile } */
|
|
+/* Verify that relaxed atomic stores use simple store instuctions. */
|
|
+/* { dg-final { scan-assembler-not "amoswap" } } */
|
|
+
|
|
+void
|
|
+foo(int bar, int baz)
|
|
+{
|
|
+ __atomic_store_n(&bar, baz, __ATOMIC_RELAXED);
|
|
+}
|
|
--
|
|
2.39.3
|
|
|