58 lines
1.6 KiB
Diff
58 lines
1.6 KiB
Diff
From 36a84e538bb9d3feb1762200074f39a1e9ff4fce Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Fri, 7 Apr 2023 10:44:09 -0700
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Subject: [PATCH] RISC-V: Weaken mem_thread_fence
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This change brings atomic fences in line with table A.6 of the ISA
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manual.
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Relax mem_thread_fence according to the memmodel given.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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gcc/ChangeLog:
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* config/riscv/sync.md (mem_thread_fence_1): Change fence
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depending on the given memory model.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/sync.md | 16 +++++++++++++---
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1 file changed, 13 insertions(+), 3 deletions(-)
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diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
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index 3e6345e83a35..ba132d8a1cea 100644
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--- a/gcc/config/riscv/sync.md
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+++ b/gcc/config/riscv/sync.md
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@@ -45,14 +45,24 @@
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DONE;
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})
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-;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
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-;; conservatively emit a full FENCE.
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(define_insn "mem_thread_fence_1"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
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(match_operand:SI 1 "const_int_operand" "")] ;; model
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""
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- "fence\tiorw,iorw")
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+ {
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+ enum memmodel model = (enum memmodel) INTVAL (operands[1]);
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+ model = memmodel_base (model);
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+ if (model == MEMMODEL_SEQ_CST)
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+ return "fence\trw,rw";
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+ else if (model == MEMMODEL_ACQ_REL)
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+ return "fence.tso";
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+ else if (model == MEMMODEL_ACQUIRE)
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+ return "fence\tr,rw";
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+ else if (model == MEMMODEL_RELEASE)
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+ return "fence\trw,w";
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+ }
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+ [(set (attr "length") (const_int 4))])
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;; Atomic memory operations.
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--
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2.39.3
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