115 lines
3.1 KiB
Diff
115 lines
3.1 KiB
Diff
2007-07-13 Andrew Haley <aph@redhat.com>
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* libgcj.ver: Add __gcj_personality_sj0.
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2007-07-11 Andrew Haley <aph@redhat.com>
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* configure.host (arm*-linux-gnu): New.
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* sysdep/arm/locks.h: New.
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--- libjava/configure.host (revision 126621)
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+++ libjava/configure.host (revision 126623)
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@@ -82,6 +82,10 @@ case "${host}" in
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enable_getenv_properties_default=no
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enable_main_args_default=no
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;;
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+ arm*-linux-gnu)
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+ libgcj_interpreter=yes
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+ sysdeps_dir=arm
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+ ;;
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mips-tx39-*|mipstx39-unknown-*)
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libgcj_flags="${libgcj_flags} -G 0"
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LDFLAGS="$LDFLAGS -Tjmr3904dram.ld"
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--- libjava/libgcj.ver (revision 126621)
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+++ libjava/libgcj.ver (revision 126623)
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@@ -2,6 +2,6 @@
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# symbols in libgcj.so.
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{
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- global: Jv*; _Jv_*; __gcj_personality_v0; _Z*;
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+ global: Jv*; _Jv_*; __gcj_personality_v0; __gcj_personality_sj0; _Z*;
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local: *;
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};
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--- libjava/sysdep/arm/locks.h (revision 0)
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+++ libjava/sysdep/arm/locks.h (revision 126623)
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@@ -0,0 +1,79 @@
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+// locks.h - Thread synchronization primitives. ARM implementation.
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+
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+/* Copyright (C) 2007 Free Software Foundation
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+
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+ This file is part of libgcj.
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+
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+This software is copyrighted work licensed under the terms of the
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+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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+details. */
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+
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+#ifndef __SYSDEP_LOCKS_H__
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+#define __SYSDEP_LOCKS_H__
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+
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+typedef size_t obj_addr_t; /* Integer type big enough for object */
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+ /* address. */
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+
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+/* Atomic compare and exchange. These sequences are not actually
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+ atomic; there is a race if *ADDR != OLD_VAL and we are preempted
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+ between the two swaps. However, they are very close to atomic, and
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+ are the best that a pre-ARMv6 implementation can do without
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+ operating system support. LinuxThreads has been using these
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+ sequences for many years. */
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+
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+inline static bool
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+compare_and_swap(volatile obj_addr_t *addr,
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+ obj_addr_t old_val,
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+ obj_addr_t new_val)
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+{
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+ volatile obj_addr_t result, tmp;
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+ __asm__ ("\n"
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+ "0: ldr %[tmp],[%[addr]]\n"
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+ " cmp %[tmp],%[old_val]\n"
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+ " movne %[result],#0\n"
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+ " bne 1f\n"
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+ " swp %[result],%[new_val],[%[addr]]\n"
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+ " cmp %[tmp],%[result]\n"
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+ " swpne %[tmp],%[result],[%[addr]]\n"
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+ " bne 0b\n"
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+ " mov %[result],#1\n"
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+ "1:"
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+ : [result] "=&r" (result), [tmp] "=&r" (tmp)
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+ : [addr] "r" (addr), [new_val] "r" (new_val), [old_val] "r" (old_val)
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+ : "cc", "memory");
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+
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+ return result;
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+}
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+
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+inline static void
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+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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+{
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+ __asm__ __volatile__("" : : : "memory");
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+ *(addr) = new_val;
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+}
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+
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+inline static bool
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+compare_and_swap_release(volatile obj_addr_t *addr,
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+ obj_addr_t old,
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+ obj_addr_t new_val)
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+{
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+ return compare_and_swap(addr, old, new_val);
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+}
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+
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+// Ensure that subsequent instructions do not execute on stale
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+// data that was loaded from memory before the barrier.
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+inline static void
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+read_barrier()
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+{
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+
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+// Ensure that prior stores to memory are completed with respect to other
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+// processors.
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+inline static void
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+write_barrier()
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+{
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+
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+#endif
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