42 lines
1.2 KiB
Diff
42 lines
1.2 KiB
Diff
From 687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6 Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Wed, 5 Apr 2023 09:47:05 -0700
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Subject: [PATCH] RISC-V: Add AMO release bits
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This patch sets the relevant .rl bits on amo operations.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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gcc/ChangeLog:
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* config/riscv/riscv.cc (riscv_print_operand): Change behavior
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of %A to include release bits.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/riscv.cc | 7 ++++++-
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1 file changed, 6 insertions(+), 1 deletion(-)
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
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index 11b897aca5c4..df55c427b1b3 100644
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--- a/gcc/config/riscv/riscv.cc
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+++ b/gcc/config/riscv/riscv.cc
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@@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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break;
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case 'A':
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- if (riscv_memmodel_needs_amo_acquire (model))
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+ if (riscv_memmodel_needs_amo_acquire (model)
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+ && riscv_memmodel_needs_release_fence (model))
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+ fputs (".aqrl", file);
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+ else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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+ else if (riscv_memmodel_needs_release_fence (model))
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+ fputs (".rl", file);
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break;
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case 'F':
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--
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2.39.3
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