50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From 0180b20de73778fe1e67060f66c7f47630aeb949 Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Wed, 5 Apr 2023 09:46:37 -0700
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Subject: [PATCH] RISC-V: Enforce atomic compare_exchange SEQ_CST
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This patch enforces SEQ_CST for atomic compare_exchange ops.
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Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
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recommended by table A.6 of the ISA manual.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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gcc/ChangeLog:
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* config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
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FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
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pair.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/sync.md | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
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index 0c83ef046070..5620d6ffa587 100644
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--- a/gcc/config/riscv/sync.md
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+++ b/gcc/config/riscv/sync.md
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@@ -297,9 +297,16 @@
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UNSPEC_COMPARE_AND_SWAP))
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(clobber (match_scratch:GPR 6 "=&r"))]
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"TARGET_ATOMIC"
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- "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
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+ {
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+ return "1:\;"
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+ "lr.<amo>.aqrl\t%0,%1\;"
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+ "bne\t%0,%z2,1f\;"
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+ "sc.<amo>.rl\t%6,%z3,%1\;"
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+ "bnez\t%6,1b\;"
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+ "1:";
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+ }
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[(set_attr "type" "atomic")
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- (set (attr "length") (const_int 20))])
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+ (set (attr "length") (const_int 16))])
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:SI 0 "register_operand" "") ;; bool output
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--
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2.39.3
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