David Abdurachmanov
71ec449f44
Backport 16 patches (riscv64 specific) from the current gcc13 upstream branch. Most of these are memory model related. Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
88 lines
2.7 KiB
Diff
88 lines
2.7 KiB
Diff
From 74abe200bc9b06e10f0f3cad74f11da4fae90cd3 Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Wed, 5 Apr 2023 09:56:33 -0700
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Subject: [PATCH] RISC-V: Strengthen atomic stores
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This change makes atomic stores strictly stronger than table A.6 of the
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ISA manual. This mapping makes the overall patchset compatible with
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table A.7 as well.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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PR target/89835
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gcc/ChangeLog:
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* config/riscv/sync.md (atomic_store<mode>): Use simple store
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instruction in combination with fence(s).
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gcc/testsuite/ChangeLog:
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* gcc.target/riscv/pr89835.c: New test.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/sync.md | 21 ++++++++++++++++++---
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gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++
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2 files changed, 27 insertions(+), 3 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c
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diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
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index 5620d6ffa587..1acb78a9ae4c 100644
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--- a/gcc/config/riscv/sync.md
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+++ b/gcc/config/riscv/sync.md
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@@ -56,7 +56,9 @@
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;; Atomic memory operations.
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-;; Implement atomic stores with amoswap. Fall back to fences for atomic loads.
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+;; Implement atomic stores with conservative fences. Fall back to fences for
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+;; atomic loads.
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+;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7.
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(define_insn "atomic_store<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "=A")
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(unspec_volatile:GPR
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@@ -64,9 +66,22 @@
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPEC_ATOMIC_STORE))]
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"TARGET_ATOMIC"
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- "%F2amoswap.<amo>%A2 zero,%z1,%0"
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+ {
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+ enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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+ model = memmodel_base (model);
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+
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+ if (model == MEMMODEL_SEQ_CST)
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+ return "fence\trw,w\;"
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+ "s<amo>\t%z1,%0\;"
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+ "fence\trw,rw";
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+ if (model == MEMMODEL_RELEASE)
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+ return "fence\trw,w\;"
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+ "s<amo>\t%z1,%0";
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+ else
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+ return "s<amo>\t%z1,%0";
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+ }
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[(set_attr "type" "atomic")
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- (set (attr "length") (const_int 8))])
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+ (set (attr "length") (const_int 12))])
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(define_insn "atomic_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+A")
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diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c
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new file mode 100644
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index 000000000000..ab190e11b608
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/pr89835.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* Verify that relaxed atomic stores use simple store instuctions. */
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+/* { dg-final { scan-assembler-not "amoswap" } } */
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+
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+void
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+foo(int bar, int baz)
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+{
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+ __atomic_store_n(&bar, baz, __ATOMIC_RELAXED);
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+}
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--
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2.39.3
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