47 lines
1.7 KiB
Diff
47 lines
1.7 KiB
Diff
2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/60137
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* config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
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for VSX/Altivec vectors that land in GPR registers.
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* gcc.target/powerpc/pr60137.c: New file.
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--- gcc/config/rs6000/rs6000.md (revision 207698)
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+++ gcc/config/rs6000/rs6000.md (revision 207699)
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@@ -9963,6 +9963,15 @@ (define_insn_and_split "reload_vsx_from_
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[(set_attr "length" "12")
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(set_attr "type" "three")])
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+(define_split
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+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
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+ (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
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+ "reload_completed
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+ && (int_reg_operand (operands[0], <MODE>mode)
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+ || int_reg_operand (operands[1], <MODE>mode))"
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+ [(pc)]
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+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
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+
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;; Move SFmode to a VSX from a GPR register. Because scalar floating point
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;; type is stored internally as double precision in the VSX registers, we have
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;; to convert it from the vector format.
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--- gcc/testsuite/gcc.target/powerpc/pr60137.c (revision 0)
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+++ gcc/testsuite/gcc.target/powerpc/pr60137.c (revision 207699)
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@@ -0,0 +1,17 @@
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+/* { dg-do compile { target { powerpc*-*-* } } } */
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+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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+/* { dg-require-effective-target powerpc_p8vector_ok } */
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+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */
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+
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+/* target/60137, compiler got a 'could not split insn error'. */
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+
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+extern int target_flags;
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+extern char fixed_regs[53];
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+extern char call_used_regs[53];
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+
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+void init_reg_sets_1(void)
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+{
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+ int i;
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+ for (i = 0; i < 53; i++)
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+ fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;
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+}
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