228 lines
9.2 KiB
Diff
228 lines
9.2 KiB
Diff
From d6279ef7800d8d3c0cec208900e9c443af875bd1 Mon Sep 17 00:00:00 2001
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From: kito <kito@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Fri, 20 Sep 2019 10:41:51 +0000
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Subject: [PATCH] RISC-V: Fix more splitters accidentally calling gen_reg_rtx.
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PR target/91683
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* config/riscv/riscv-protos.h (riscv_split_symbol): New bool parameter.
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(riscv_move_integer): Likewise.
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* config/riscv/riscv.c (riscv_split_integer): Pass FALSE for new
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riscv_move_integer arg.
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(riscv_legitimize_move): Likewise.
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(riscv_force_temporary): New parameter in_splitter. Don't call
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force_reg if true.
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(riscv_unspec_offset_high): Pass FALSE for new riscv_force_temporary
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arg.
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(riscv_add_offset): Likewise.
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(riscv_split_symbol): New parameter in_splitter. Pass to
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riscv_force_temporary.
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(riscv_legitimize_address): Pass FALSE for new riscv_split_symbol
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arg.
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(riscv_move_integer): New parameter in_splitter. New local
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can_create_psuedo. Don't call riscv_split_integer or force_reg when
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in_splitter TRUE.
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(riscv_legitimize_const_move): Pass FALSE for new riscv_move_integer,
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riscv_split_symbol, and riscv_force_temporary args.
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* config/riscv/riscv.md (low<mode>+1): Pass TRUE for new
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riscv_move_integer arg.
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(low<mode>+2): Pass TRUE for new riscv_split_symbol arg.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275997 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/config/riscv/riscv-protos.h | 4 +--
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gcc/config/riscv/riscv.c | 45 ++++++++++++++++++++-------------
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gcc/config/riscv/riscv.md | 6 ++---
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4 files changed, 62 insertions(+), 22 deletions(-)
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diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
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index 8b510f87df87..5b0bbdd7cb4e 100644
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--- a/gcc/config/riscv/riscv-protos.h
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+++ b/gcc/config/riscv/riscv-protos.h
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@@ -44,10 +44,10 @@ extern int riscv_const_insns (rtx);
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extern int riscv_split_const_insns (rtx);
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extern int riscv_load_store_insns (rtx, rtx_insn *);
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extern rtx riscv_emit_move (rtx, rtx);
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-extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
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+extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool);
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extern bool riscv_split_symbol_type (enum riscv_symbol_type);
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extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
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-extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
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+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, bool);
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extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
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extern rtx riscv_subword (rtx, bool);
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extern bool riscv_split_64bit_move_p (rtx, rtx);
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diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
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index 35219956c80d..5cb295d3abba 100644
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--- a/gcc/config/riscv/riscv.c
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+++ b/gcc/config/riscv/riscv.c
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@@ -508,8 +508,8 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)
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unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
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rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode);
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- riscv_move_integer (hi, hi, hival);
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- riscv_move_integer (lo, lo, loval);
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+ riscv_move_integer (hi, hi, hival, FALSE);
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+ riscv_move_integer (lo, lo, loval, FALSE);
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hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32));
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hi = force_reg (mode, hi);
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@@ -1021,9 +1021,12 @@ riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y)
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are allowed, copy it into a new register, otherwise use DEST. */
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static rtx
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-riscv_force_temporary (rtx dest, rtx value)
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+riscv_force_temporary (rtx dest, rtx value, bool in_splitter)
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{
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- if (can_create_pseudo_p ())
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+ /* We can't call gen_reg_rtx from a splitter, because this might realloc
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+ the regno_reg_rtx array, which would invalidate reg rtx pointers in the
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+ combine undo buffer. */
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+ if (can_create_pseudo_p () && !in_splitter)
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return force_reg (Pmode, value);
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else
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{
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@@ -1082,7 +1085,7 @@ static rtx
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riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type)
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{
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addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type));
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- return riscv_force_temporary (temp, addr);
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+ return riscv_force_temporary (temp, addr, FALSE);
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}
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/* Load an entry from the GOT for a TLS GD access. */
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@@ -1130,7 +1133,8 @@ static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym)
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is guaranteed to be a legitimate address for mode MODE. */
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bool
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-riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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+riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out,
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+ bool in_splitter)
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{
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enum riscv_symbol_type symbol_type;
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@@ -1146,7 +1150,7 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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case SYMBOL_ABSOLUTE:
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{
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
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- high = riscv_force_temporary (temp, high);
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+ high = riscv_force_temporary (temp, high, in_splitter);
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*low_out = gen_rtx_LO_SUM (Pmode, high, addr);
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}
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break;
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@@ -1205,8 +1209,9 @@ riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
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overflow, so we need to force a sign-extension check. */
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high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
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offset = CONST_LOW_PART (offset);
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- high = riscv_force_temporary (temp, high);
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- reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
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+ high = riscv_force_temporary (temp, high, FALSE);
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+ reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg),
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+ FALSE);
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}
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return plus_constant (Pmode, reg, offset);
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}
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@@ -1315,7 +1320,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
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return riscv_legitimize_tls_address (x);
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/* See if the address can split into a high part and a LO_SUM. */
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- if (riscv_split_symbol (NULL, x, mode, &addr))
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+ if (riscv_split_symbol (NULL, x, mode, &addr, FALSE))
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return riscv_force_address (addr, mode);
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/* Handle BASE + OFFSET using riscv_add_offset. */
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@@ -1337,17 +1342,23 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
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/* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */
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void
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-riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
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+riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
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+ bool in_splitter)
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{
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struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
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machine_mode mode;
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int i, num_ops;
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rtx x;
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+ /* We can't call gen_reg_rtx from a splitter, because this might realloc
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+ the regno_reg_rtx array, which would invalidate reg rtx pointers in the
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+ combine undo buffer. */
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+ bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter;
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+
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mode = GET_MODE (dest);
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num_ops = riscv_build_integer (codes, value, mode);
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- if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */
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+ if (can_create_pseudo && num_ops > 2 /* not a simple constant */
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&& num_ops >= riscv_split_integer_cost (value))
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x = riscv_split_integer (value, mode);
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else
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@@ -1357,7 +1368,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
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for (i = 1; i < num_ops; i++)
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{
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- if (!can_create_pseudo_p ())
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+ if (!can_create_pseudo)
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x = riscv_emit_set (temp, x);
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else
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x = force_reg (mode, x);
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@@ -1381,12 +1392,12 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
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/* Split moves of big integers into smaller pieces. */
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if (splittable_const_int_operand (src, mode))
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{
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- riscv_move_integer (dest, dest, INTVAL (src));
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+ riscv_move_integer (dest, dest, INTVAL (src), FALSE);
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return;
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}
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/* Split moves of symbolic constants into high/low pairs. */
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- if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
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+ if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE))
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{
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riscv_emit_set (dest, src);
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return;
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@@ -1407,7 +1418,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
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if (offset != const0_rtx
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&& (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ()))
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{
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- base = riscv_force_temporary (dest, base);
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+ base = riscv_force_temporary (dest, base, FALSE);
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riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset)));
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return;
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}
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@@ -1416,7 +1427,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
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/* When using explicit relocs, constant pool references are sometimes
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not legitimate addresses. */
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- riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
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+ riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE);
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riscv_emit_move (dest, src);
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}
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diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
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index 7850c41f3c7e..e40535c9e405 100644
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--- a/gcc/config/riscv/riscv.md
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+++ b/gcc/config/riscv/riscv.md
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@@ -1284,7 +1284,7 @@
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""
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[(const_int 0)]
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{
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- riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]));
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+ riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), TRUE);
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DONE;
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})
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@@ -1293,11 +1293,11 @@
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1))
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(clobber (match_operand:P 2 "register_operand"))]
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- "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
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+ "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)"
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[(set (match_dup 0) (match_dup 3))]
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{
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riscv_split_symbol (operands[2], operands[1],
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- MAX_MACHINE_MODE, &operands[3]);
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+ MAX_MACHINE_MODE, &operands[3], TRUE);
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})
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;; 64-bit integer moves
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