157 lines
5.2 KiB
Diff
157 lines
5.2 KiB
Diff
From 35ced3822a12415f7bf7307f43c503736aa4b8e8 Mon Sep 17 00:00:00 2001
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From: David Abdurachmanov <david.abdurachmanov@gmail.com>
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Date: Wed, 23 Jan 2019 21:45:01 +0100
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Subject: [PATCH] Add RISCV support in libphobos
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Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
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---
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.../allocator/building_blocks/region.d | 3 +-
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libphobos/src/std/math.d | 61 +++++++++++++++++++
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2 files changed, 63 insertions(+), 1 deletion(-)
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diff --git a/libphobos/src/std/experimental/allocator/building_blocks/region.d b/libphobos/src/std/experimental/allocator/building_blocks/region.d
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index 80157aee7e6..ad90d17df00 100644
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--- a/libphobos/src/std/experimental/allocator/building_blocks/region.d
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+++ b/libphobos/src/std/experimental/allocator/building_blocks/region.d
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@@ -390,7 +390,8 @@ struct InSituRegion(size_t size, size_t minAlign = platformAlignment)
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else version (PPC) enum growDownwards = Yes.growDownwards;
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else version (PPC64) enum growDownwards = Yes.growDownwards;
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else version (MIPS32) enum growDownwards = Yes.growDownwards;
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- else version (MIPS64) enum growDownwards = Yes.growDownwards;
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+ else version (RISCV32) enum growDownwards = Yes.growDownwards;
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+ else version (RISCV64) enum growDownwards = Yes.growDownwards;
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else version (SPARC) enum growDownwards = Yes.growDownwards;
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else version (SystemZ) enum growDownwards = Yes.growDownwards;
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else static assert(0, "Dunno how the stack grows on this architecture.");
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diff --git a/libphobos/src/std/math.d b/libphobos/src/std/math.d
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index 7bb4d7c23db..ba9b03c4da9 100644
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--- a/libphobos/src/std/math.d
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+++ b/libphobos/src/std/math.d
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@@ -160,6 +160,8 @@ version (MIPS32) version = MIPS_Any;
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version (MIPS64) version = MIPS_Any;
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version (AArch64) version = ARM_Any;
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version (ARM) version = ARM_Any;
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+version (RISCV32) version = RISCV_Any;
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+version (RISCV64) version = RISCV_Any;
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version (D_InlineAsm_X86)
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{
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@@ -4654,6 +4656,7 @@ private:
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// The Pentium SSE2 status register is 32 bits.
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// The ARM and PowerPC FPSCR is a 32-bit register.
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// The SPARC FSR is a 32bit register (64 bits for SPARC 7 & 8, but high bits are uninteresting).
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+ // The RISC-V (32 & 64 bit) are 32-bit register.
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uint flags;
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version (CRuntime_Microsoft)
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@@ -4725,6 +4728,15 @@ private:
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return result;
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}
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}
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+ else version (RISCV_Any)
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+ {
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+ uint result = void;
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+ asm pure nothrow @nogc
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+ {
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+ "frflags %0" : "=r" (result);
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+ }
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+ return result;
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+ }
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else
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assert(0, "Not yet supported");
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}
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@@ -4799,6 +4811,15 @@ private:
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}
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}
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}
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+ else version (RISCV_Any)
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+ {
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+ uint oldValues = void;
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+ uint newValues = 0x0;
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+ asm pure nothrow @nogc
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+ {
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+ "fsflags %0 %1" : "=r" (oldValues) : "r" (newValues);
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+ }
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+ }
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else
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assert(0, "Not yet supported");
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}
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@@ -4968,6 +4989,10 @@ else version (PPC_Any)
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{
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version = IeeeFlagsSupport;
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}
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+else version (RISCV_Any)
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+{
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+ version = IeeeFlagsSupport;
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+}
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else version (MIPS_Any)
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{
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version = IeeeFlagsSupport;
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@@ -5162,6 +5187,21 @@ struct FloatingPointControl
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| inexactException,
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}
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}
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+ else version (RISCV_Any)
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+ {
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+ enum : ExceptionMask
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+ {
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+ inexactException = 0x01,
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+ divByZeroException = 0x02,
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+ underflowException = 0x04,
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+ overflowException = 0x08,
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+ invalidException = 0x10,
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+ severeExceptions = overflowException | divByZeroException
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+ | invalidException,
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+ allExceptions = severeExceptions | underflowException
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+ | inexactException,
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+ }
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+ }
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else version (SPARC64)
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{
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enum : ExceptionMask
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@@ -5292,6 +5332,10 @@ private:
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{
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alias ControlState = uint;
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}
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+ else version (RISCV_Any)
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+ {
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+ alias ControlState = uint;
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+ }
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else version (SPARC64)
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{
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alias ControlState = ulong;
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@@ -5359,6 +5403,15 @@ private:
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}
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return cont;
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}
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+ else version (RISCV_Any)
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+ {
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+ ControlState cont;
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+ asm pure nothrow @nogc
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+ {
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+ "frcsr %0" : "=r" (cont);
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+ }
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+ return cont;
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+ }
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else
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assert(0, "Not yet supported");
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}
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@@ -5444,6 +5497,14 @@ private:
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}
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}
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}
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+ else version (RISCV_Any)
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+ {
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+ uint oldState = void;
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+ asm pure nothrow @nogc
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+ {
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+ "fscsr %0, %1;" : "=r" (oldState) : "r" (newState);
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+ }
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+ }
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else
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assert(0, "Not yet supported");
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}
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--
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2.20.1
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