240 lines
11 KiB
Diff
240 lines
11 KiB
Diff
From ffd676ef2c9849231626a532343c7ec908558c33 Mon Sep 17 00:00:00 2001
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From: yulong <shiyulong@iscas.ac.cn>
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Date: Tue, 8 Aug 2023 12:12:32 +0800
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Subject: [PATCH] RISC-V: Fix a bug that causes an error insn.
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MIME-Version: 1.0
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Content-Type: text/plain; charset=utf8
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Content-Transfer-Encoding: 8bit
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I test the following rvv intrinsics.
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vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
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}
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And I got an error info,t hat is error:
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unrecognizable insn:(insn 17 16 18 2
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(set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI
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(unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int æ¥ [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE
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(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI æ¥ zero)] UNSPEC_VUNDEF)
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(reg/v:RVVMF64BI 137 [ mask ]))
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(unspec:RVVM1DI[(reg:sI æ¥ zero)] UNSPEC_VUNDEF)))
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This patch fix it.
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gcc/ChangeLog:
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* config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.
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gcc/testsuite/ChangeLog:
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* gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
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* gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
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* gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
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* gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
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* gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
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* gcc.target/riscv/rvv/base/vslide1up-3.c: New test.
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---
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gcc/config/riscv/riscv-v.cc | 5 ++---
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.../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++
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.../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++
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.../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++
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.../gcc.target/riscv/rvv/base/vslide1up-1.c | 22 +++++++++++++++++++
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.../gcc.target/riscv/rvv/base/vslide1up-2.c | 22 +++++++++++++++++++
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.../gcc.target/riscv/rvv/base/vslide1up-3.c | 22 +++++++++++++++++++
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7 files changed, 134 insertions(+), 3 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
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diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
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index 392f5d02e17c..722ed27bd267 100644
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--- a/gcc/config/riscv/riscv-v.cc
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+++ b/gcc/config/riscv/riscv-v.cc
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@@ -701,9 +701,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
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CONSTM1_RTX (demote_mask_mode), merge, temp,
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demote_scalar_op2, vl_x2, ta, ma, ops[8]));
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- if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
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- return true;
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- else
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+ if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
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+ && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]))))
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emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
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force_vector_length_operand (ops[5]), ops[6],
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ops[8]));
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
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new file mode 100644
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index 000000000000..541745be2a1e
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
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new file mode 100644
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index 000000000000..9b5a240a9e69
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
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\ No newline at end of file
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
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new file mode 100644
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index 000000000000..7b05c85a243a
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
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\ No newline at end of file
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
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new file mode 100644
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index 000000000000..74e8e5e63f70
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
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new file mode 100644
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index 000000000000..e7e2ee950c73
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
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new file mode 100644
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index 000000000000..b0b3af24e644
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
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@@ -0,0 +1,22 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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+
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+#include "riscv_vector.h"
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+
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+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
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+}
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+
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+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
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+}
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+
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+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
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+}
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+
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+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
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+ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
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+}
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+
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+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
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--
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2.39.3
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