70 lines
2.0 KiB
Diff
70 lines
2.0 KiB
Diff
From 0e42ac31fdeffdcec22f1935534693d4cef62e0b Mon Sep 17 00:00:00 2001
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From: Patrick O'Neill <patrick@rivosinc.com>
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Date: Fri, 7 Apr 2023 15:14:17 -0700
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Subject: [PATCH] RISC-V: Weaken atomic loads
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This change brings atomic loads in line with table A.6 of the ISA
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manual.
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2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
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gcc/ChangeLog:
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* config/riscv/sync.md (atomic_load<mode>): Implement atomic
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load mapping.
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Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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---
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gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++--
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1 file changed, 26 insertions(+), 2 deletions(-)
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diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
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index ba132d8a1cea..6e7c762ac577 100644
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--- a/gcc/config/riscv/sync.md
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+++ b/gcc/config/riscv/sync.md
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@@ -26,6 +26,7 @@
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UNSPEC_SYNC_OLD_OP_SUBWORD
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UNSPEC_SYNC_EXCHANGE
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UNSPEC_SYNC_EXCHANGE_SUBWORD
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+ UNSPEC_ATOMIC_LOAD
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UNSPEC_ATOMIC_STORE
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UNSPEC_MEMORY_BARRIER
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])
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@@ -66,8 +67,31 @@
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;; Atomic memory operations.
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-;; Implement atomic stores with conservative fences. Fall back to fences for
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-;; atomic loads.
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+(define_insn "atomic_load<mode>"
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+ [(set (match_operand:GPR 0 "register_operand" "=r")
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+ (unspec_volatile:GPR
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+ [(match_operand:GPR 1 "memory_operand" "A")
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+ (match_operand:SI 2 "const_int_operand")] ;; model
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+ UNSPEC_ATOMIC_LOAD))]
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+ "TARGET_ATOMIC"
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+ {
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+ enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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+ model = memmodel_base (model);
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+
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+ if (model == MEMMODEL_SEQ_CST)
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+ return "fence\trw,rw\;"
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+ "l<amo>\t%0,%1\;"
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+ "fence\tr,rw";
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+ if (model == MEMMODEL_ACQUIRE)
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+ return "l<amo>\t%0,%1\;"
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+ "fence\tr,rw";
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+ else
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+ return "l<amo>\t%0,%1";
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+ }
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+ [(set_attr "type" "atomic")
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+ (set (attr "length") (const_int 12))])
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+
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+;; Implement atomic stores with conservative fences.
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;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7.
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(define_insn "atomic_store<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "=A")
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--
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2.39.3
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