From 687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6 Mon Sep 17 00:00:00 2001 From: Patrick O'Neill Date: Wed, 5 Apr 2023 09:47:05 -0700 Subject: [PATCH] RISC-V: Add AMO release bits This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 11b897aca5c4..df55c427b1b3 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': -- 2.39.3