2014-02-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60137
	* config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
	for VSX/Altivec vectors that land in GPR registers.

	* gcc.target/powerpc/pr60137.c: New file.

--- gcc/config/rs6000/rs6000.md	(revision 207698)
+++ gcc/config/rs6000/rs6000.md	(revision 207699)
@@ -9963,6 +9963,15 @@ (define_insn_and_split "reload_vsx_from_
   [(set_attr "length" "12")
    (set_attr "type" "three")])
 
+(define_split
+  [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
+	(match_operand:FMOVE128_GPR 1 "input_operand" ""))]
+  "reload_completed
+   && (int_reg_operand (operands[0], <MODE>mode)
+       || int_reg_operand (operands[1], <MODE>mode))"
+  [(pc)]
+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+
 ;; Move SFmode to a VSX from a GPR register.  Because scalar floating point
 ;; type is stored internally as double precision in the VSX registers, we have
 ;; to convert it from the vector format.
--- gcc/testsuite/gcc.target/powerpc/pr60137.c	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr60137.c	(revision 207699)
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */
+
+/* target/60137, compiler got a 'could not split insn error'.  */
+
+extern int target_flags;
+extern char fixed_regs[53];
+extern char call_used_regs[53];
+
+void init_reg_sets_1(void)
+{
+  int i;
+  for (i = 0; i < 53; i++)
+    fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;
+}