From 35ced3822a12415f7bf7307f43c503736aa4b8e8 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Wed, 23 Jan 2019 21:45:01 +0100
Subject: [PATCH] Add RISCV support in libphobos

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
 .../allocator/building_blocks/region.d        |  3 +-
 libphobos/src/std/math.d                      | 61 +++++++++++++++++++
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/libphobos/src/std/experimental/allocator/building_blocks/region.d b/libphobos/src/std/experimental/allocator/building_blocks/region.d
index 80157aee7e6..ad90d17df00 100644
--- a/libphobos/src/std/experimental/allocator/building_blocks/region.d
+++ b/libphobos/src/std/experimental/allocator/building_blocks/region.d
@@ -390,7 +390,8 @@ struct InSituRegion(size_t size, size_t minAlign = platformAlignment)
     else version (PPC) enum growDownwards = Yes.growDownwards;
     else version (PPC64) enum growDownwards = Yes.growDownwards;
     else version (MIPS32) enum growDownwards = Yes.growDownwards;
-    else version (MIPS64) enum growDownwards = Yes.growDownwards;
+    else version (RISCV32) enum growDownwards = Yes.growDownwards;
+    else version (RISCV64) enum growDownwards = Yes.growDownwards;
     else version (SPARC) enum growDownwards = Yes.growDownwards;
     else version (SystemZ) enum growDownwards = Yes.growDownwards;
     else static assert(0, "Dunno how the stack grows on this architecture.");
diff --git a/libphobos/src/std/math.d b/libphobos/src/std/math.d
index 7bb4d7c23db..ba9b03c4da9 100644
--- a/libphobos/src/std/math.d
+++ b/libphobos/src/std/math.d
@@ -160,6 +160,8 @@ version (MIPS32)    version = MIPS_Any;
 version (MIPS64)    version = MIPS_Any;
 version (AArch64)   version = ARM_Any;
 version (ARM)       version = ARM_Any;
+version (RISCV32)   version = RISCV_Any;
+version (RISCV64)   version = RISCV_Any;
 
 version (D_InlineAsm_X86)
 {
@@ -4654,6 +4656,7 @@ private:
     // The Pentium SSE2 status register is 32 bits.
     // The ARM and PowerPC FPSCR is a 32-bit register.
     // The SPARC FSR is a 32bit register (64 bits for SPARC 7 & 8, but high bits are uninteresting).
+    // The RISC-V (32 & 64 bit) are 32-bit register.
     uint flags;
 
     version (CRuntime_Microsoft)
@@ -4725,6 +4728,15 @@ private:
                     return result;
                 }
             }
+            else version (RISCV_Any)
+            {
+                uint result = void;
+                asm pure nothrow @nogc
+                {
+                    "frflags %0" : "=r" (result);
+                }
+                return result;
+            }
             else
                 assert(0, "Not yet supported");
         }
@@ -4799,6 +4811,15 @@ private:
                     }
                 }
             }
+            else version (RISCV_Any)
+            {
+                uint oldValues = void;
+                uint newValues = 0x0;
+                asm pure nothrow @nogc
+                {
+                    "fsflags %0 %1" : "=r" (oldValues) : "r" (newValues);
+                }
+            }
             else
                 assert(0, "Not yet supported");
         }
@@ -4968,6 +4989,10 @@ else version (PPC_Any)
 {
     version = IeeeFlagsSupport;
 }
+else version (RISCV_Any)
+{
+    version = IeeeFlagsSupport;
+}
 else version (MIPS_Any)
 {
     version = IeeeFlagsSupport;
@@ -5162,6 +5187,21 @@ struct FloatingPointControl
                                  | inexactException,
         }
     }
+    else version (RISCV_Any)
+    {
+        enum : ExceptionMask
+        {
+            inexactException      = 0x01,
+            divByZeroException    = 0x02,
+            underflowException    = 0x04,
+            overflowException     = 0x08,
+            invalidException      = 0x10,
+            severeExceptions   = overflowException | divByZeroException
+                                 | invalidException,
+            allExceptions      = severeExceptions | underflowException
+                                 | inexactException,
+        }
+    }
     else version (SPARC64)
     {
         enum : ExceptionMask
@@ -5292,6 +5332,10 @@ private:
     {
         alias ControlState = uint;
     }
+    else version (RISCV_Any)
+    {
+        alias ControlState = uint;
+    }
     else version (SPARC64)
     {
         alias ControlState = ulong;
@@ -5359,6 +5403,15 @@ private:
                 }
                 return cont;
             }
+            else version (RISCV_Any)
+            {
+                ControlState cont;
+                asm pure nothrow @nogc
+                {
+                    "frcsr %0" : "=r" (cont);
+                }
+                return cont;
+            }
             else
                 assert(0, "Not yet supported");
         }
@@ -5444,6 +5497,14 @@ private:
                     }
                 }
             }
+            else version (RISCV_Any)
+            {
+                uint oldState = void;
+                asm pure nothrow @nogc
+                {
+                    "fscsr %0, %1;" : "=r" (oldState) : "r" (newState);
+                }
+            }
             else
                 assert(0, "Not yet supported");
         }
-- 
2.20.1