From f961a694a2b0c6241063f727cf379494a4ca9f68 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Sat, 21 Sep 2019 16:52:30 +0300 Subject: [PATCH] Add 2 RISC-V backports from upstream These are already committed upstream, but not yet in the official Fedora. Signed-off-by: David Abdurachmanov --- ...b75646ccb308bf316e0b3a7873b809d1a64a.patch | 220 +++++++++++++++++ ...9ef7800d8d3c0cec208900e9c443af875bd1.patch | 227 ++++++++++++++++++ gcc.spec | 13 +- 3 files changed, 459 insertions(+), 1 deletion(-) create mode 100644 6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch create mode 100644 d6279ef7800d8d3c0cec208900e9c443af875bd1.patch diff --git a/6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch b/6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch new file mode 100644 index 0000000..2a1cc68 --- /dev/null +++ b/6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch @@ -0,0 +1,220 @@ +From 6aafb75646ccb308bf316e0b3a7873b809d1a64a Mon Sep 17 00:00:00 2001 +From: kito +Date: Thu, 19 Sep 2019 06:38:23 +0000 +Subject: [PATCH] RISC-V: Fix bad insn splits with paradoxical subregs. + +Shifting by more than the size of a SUBREG_REG doesn't work, so we either +need to disable splits if an input is paradoxical, or else we need to +generate a clean temporary for intermediate results. + +Jakub wrote the first version of this patch, so gets primary credit for it. + + gcc/ + PR target/91635 + * config/riscv/riscv.md (zero_extendsidi2, zero_extendhi2, + extend2): Don't split if + paradoxical_subreg_p (operands[0]). + (*lshrsi3_zero_extend_3+1, *lshrsi3_zero_extend_3+2): Add clobber and + use as intermediate value. + + gcc/testsuite/ + PR target/91635 + * gcc.c-torture/execute/pr91635.c: New test. + * gcc.target/riscv/shift-shift-4.c: New test. + * gcc.target/riscv/shift-shift-5.c: New test. + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275929 138bc75d-0d04-0410-961f-82ee72b054a4 +--- + gcc/ChangeLog | 13 +++++ + gcc/config/riscv/riscv.md | 30 +++++++--- + gcc/testsuite/ChangeLog | 11 ++++ + gcc/testsuite/gcc.c-torture/execute/pr91635.c | 57 +++++++++++++++++++ + .../gcc.target/riscv/shift-shift-4.c | 13 +++++ + .../gcc.target/riscv/shift-shift-5.c | 16 ++++++ + 6 files changed, 131 insertions(+), 9 deletions(-) + create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr91635.c + create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-5.c + +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index a8bac170e72f..7850c41f3c7e 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -1051,7 +1051,9 @@ + "@ + # + lwu\t%0,%1" +- "&& reload_completed && REG_P (operands[1])" ++ "&& reload_completed ++ && REG_P (operands[1]) ++ && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) + (ashift:DI (match_dup 1) (const_int 32))) + (set (match_dup 0) +@@ -1068,7 +1070,9 @@ + "@ + # + lhu\t%0,%1" +- "&& reload_completed && REG_P (operands[1])" ++ "&& reload_completed ++ && REG_P (operands[1]) ++ && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) +@@ -1117,7 +1121,9 @@ + "@ + # + l\t%0,%1" +- "&& reload_completed && REG_P (operands[1])" ++ "&& reload_completed ++ && REG_P (operands[1]) ++ && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] + { +@@ -1765,15 +1771,20 @@ + ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into + ;; two logical shifts. Otherwise it requires 3 instructions: lui, + ;; xor/addi/srli, and. ++ ++;; Generating a temporary for the shift output gives better combiner results; ++;; and also fixes a problem where op0 could be a paradoxical reg and shifting ++;; by amounts larger than the size of the SUBREG_REG doesn't work. + (define_split + [(set (match_operand:GPR 0 "register_operand") + (and:GPR (match_operand:GPR 1 "register_operand") +- (match_operand:GPR 2 "p2m1_shift_operand")))] ++ (match_operand:GPR 2 "p2m1_shift_operand"))) ++ (clobber (match_operand:GPR 3 "register_operand"))] + "" +- [(set (match_dup 0) ++ [(set (match_dup 3) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) +- (lshiftrt:GPR (match_dup 0) (match_dup 2)))] ++ (lshiftrt:GPR (match_dup 3) (match_dup 2)))] + { + /* Op2 is a VOIDmode constant, so get the mode size from op1. */ + operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])) +@@ -1785,12 +1796,13 @@ + (define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (match_operand:DI 1 "register_operand") +- (match_operand:DI 2 "high_mask_shift_operand")))] ++ (match_operand:DI 2 "high_mask_shift_operand"))) ++ (clobber (match_operand:DI 3 "register_operand"))] + "TARGET_64BIT" +- [(set (match_dup 0) ++ [(set (match_dup 3) + (lshiftrt:DI (match_dup 1) (match_dup 2))) + (set (match_dup 0) +- (ashift:DI (match_dup 0) (match_dup 2)))] ++ (ashift:DI (match_dup 3) (match_dup 2)))] + { + operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2]))); + }) +diff --git a/gcc/testsuite/gcc.c-torture/execute/pr91635.c b/gcc/testsuite/gcc.c-torture/execute/pr91635.c +new file mode 100644 +index 000000000000..878a491fc360 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/pr91635.c +@@ -0,0 +1,57 @@ ++/* PR target/91635 */ ++ ++#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \ ++ && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 ++unsigned short b, c; ++int u, v, w, x; ++ ++__attribute__ ((noipa)) int ++foo (unsigned short c) ++{ ++ c <<= __builtin_add_overflow (-c, -1, &b); ++ c >>= 1; ++ return c; ++} ++ ++__attribute__ ((noipa)) int ++bar (unsigned short b) ++{ ++ b <<= -14 & 15; ++ b = b >> -~1; ++ return b; ++} ++ ++__attribute__ ((noipa)) int ++baz (unsigned short e) ++{ ++ e <<= 1; ++ e >>= __builtin_add_overflow (8719476735, u, &v); ++ return e; ++} ++ ++__attribute__ ((noipa)) int ++qux (unsigned int e) ++{ ++ c = ~1; ++ c *= e; ++ c = c >> (-15 & 5); ++ return c + w + x; ++} ++#endif ++ ++int ++main () ++{ ++#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \ ++ && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 ++ if (foo (0xffff) != 0x7fff) ++ __builtin_abort (); ++ if (bar (5) != 5) ++ __builtin_abort (); ++ if (baz (~0) != 0x7fff) ++ __builtin_abort (); ++ if (qux (2) != 0x7ffe) ++ __builtin_abort (); ++#endif ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c +new file mode 100644 +index 000000000000..72a45ee87ae6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */ ++ ++/* One zero-extend shift can be eliminated by modifying the constant in the ++ greater than test. Started working after modifying the splitter ++ lshrsi3_zero_extend_3+1 to use a temporary reg for the first split dest. */ ++int ++sub (int i) ++{ ++ i &= 0x7fffffff; ++ return i > 0x7f800000; ++} ++/* { dg-final { scan-assembler-not "srli" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c +new file mode 100644 +index 000000000000..5b2ae89a471d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ ++ ++/* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST ++ note. */ ++unsigned long ++sub (long l) ++{ ++ union u { ++ struct s { int a : 19; unsigned int b : 13; int x; } s; ++ long l; ++ } u; ++ u.l = l; ++ return u.s.b; ++} ++/* { dg-final { scan-assembler "srliw" } } */ diff --git a/d6279ef7800d8d3c0cec208900e9c443af875bd1.patch b/d6279ef7800d8d3c0cec208900e9c443af875bd1.patch new file mode 100644 index 0000000..f42ab0e --- /dev/null +++ b/d6279ef7800d8d3c0cec208900e9c443af875bd1.patch @@ -0,0 +1,227 @@ +From d6279ef7800d8d3c0cec208900e9c443af875bd1 Mon Sep 17 00:00:00 2001 +From: kito +Date: Fri, 20 Sep 2019 10:41:51 +0000 +Subject: [PATCH] RISC-V: Fix more splitters accidentally calling gen_reg_rtx. + + PR target/91683 + * config/riscv/riscv-protos.h (riscv_split_symbol): New bool parameter. + (riscv_move_integer): Likewise. + * config/riscv/riscv.c (riscv_split_integer): Pass FALSE for new + riscv_move_integer arg. + (riscv_legitimize_move): Likewise. + (riscv_force_temporary): New parameter in_splitter. Don't call + force_reg if true. + (riscv_unspec_offset_high): Pass FALSE for new riscv_force_temporary + arg. + (riscv_add_offset): Likewise. + (riscv_split_symbol): New parameter in_splitter. Pass to + riscv_force_temporary. + (riscv_legitimize_address): Pass FALSE for new riscv_split_symbol + arg. + (riscv_move_integer): New parameter in_splitter. New local + can_create_psuedo. Don't call riscv_split_integer or force_reg when + in_splitter TRUE. + (riscv_legitimize_const_move): Pass FALSE for new riscv_move_integer, + riscv_split_symbol, and riscv_force_temporary args. + * config/riscv/riscv.md (low+1): Pass TRUE for new + riscv_move_integer arg. + (low+2): Pass TRUE for new riscv_split_symbol arg. + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275997 138bc75d-0d04-0410-961f-82ee72b054a4 +--- + gcc/config/riscv/riscv-protos.h | 4 +-- + gcc/config/riscv/riscv.c | 45 ++++++++++++++++++++------------- + gcc/config/riscv/riscv.md | 6 ++--- + 4 files changed, 62 insertions(+), 22 deletions(-) + +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index 8b510f87df87..5b0bbdd7cb4e 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -44,10 +44,10 @@ extern int riscv_const_insns (rtx); + extern int riscv_split_const_insns (rtx); + extern int riscv_load_store_insns (rtx, rtx_insn *); + extern rtx riscv_emit_move (rtx, rtx); +-extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); ++extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool); + extern bool riscv_split_symbol_type (enum riscv_symbol_type); + extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); +-extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT); ++extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, bool); + extern bool riscv_legitimize_move (machine_mode, rtx, rtx); + extern rtx riscv_subword (rtx, bool); + extern bool riscv_split_64bit_move_p (rtx, rtx); +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index 35219956c80d..5cb295d3abba 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -508,8 +508,8 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) + unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); + rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); + +- riscv_move_integer (hi, hi, hival); +- riscv_move_integer (lo, lo, loval); ++ riscv_move_integer (hi, hi, hival, FALSE); ++ riscv_move_integer (lo, lo, loval, FALSE); + + hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); + hi = force_reg (mode, hi); +@@ -1021,9 +1021,12 @@ riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) + are allowed, copy it into a new register, otherwise use DEST. */ + + static rtx +-riscv_force_temporary (rtx dest, rtx value) ++riscv_force_temporary (rtx dest, rtx value, bool in_splitter) + { +- if (can_create_pseudo_p ()) ++ /* We can't call gen_reg_rtx from a splitter, because this might realloc ++ the regno_reg_rtx array, which would invalidate reg rtx pointers in the ++ combine undo buffer. */ ++ if (can_create_pseudo_p () && !in_splitter) + return force_reg (Pmode, value); + else + { +@@ -1082,7 +1085,7 @@ static rtx + riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) + { + addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); +- return riscv_force_temporary (temp, addr); ++ return riscv_force_temporary (temp, addr, FALSE); + } + + /* Load an entry from the GOT for a TLS GD access. */ +@@ -1130,7 +1133,8 @@ static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym) + is guaranteed to be a legitimate address for mode MODE. */ + + bool +-riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) ++riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out, ++ bool in_splitter) + { + enum riscv_symbol_type symbol_type; + +@@ -1146,7 +1150,7 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) + case SYMBOL_ABSOLUTE: + { + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); +- high = riscv_force_temporary (temp, high); ++ high = riscv_force_temporary (temp, high, in_splitter); + *low_out = gen_rtx_LO_SUM (Pmode, high, addr); + } + break; +@@ -1205,8 +1209,9 @@ riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) + overflow, so we need to force a sign-extension check. */ + high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); + offset = CONST_LOW_PART (offset); +- high = riscv_force_temporary (temp, high); +- reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); ++ high = riscv_force_temporary (temp, high, FALSE); ++ reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg), ++ FALSE); + } + return plus_constant (Pmode, reg, offset); + } +@@ -1315,7 +1320,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, + return riscv_legitimize_tls_address (x); + + /* See if the address can split into a high part and a LO_SUM. */ +- if (riscv_split_symbol (NULL, x, mode, &addr)) ++ if (riscv_split_symbol (NULL, x, mode, &addr, FALSE)) + return riscv_force_address (addr, mode); + + /* Handle BASE + OFFSET using riscv_add_offset. */ +@@ -1337,17 +1342,23 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, + /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */ + + void +-riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) ++riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, ++ bool in_splitter) + { + struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; + machine_mode mode; + int i, num_ops; + rtx x; + ++ /* We can't call gen_reg_rtx from a splitter, because this might realloc ++ the regno_reg_rtx array, which would invalidate reg rtx pointers in the ++ combine undo buffer. */ ++ bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter; ++ + mode = GET_MODE (dest); + num_ops = riscv_build_integer (codes, value, mode); + +- if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ ++ if (can_create_pseudo && num_ops > 2 /* not a simple constant */ + && num_ops >= riscv_split_integer_cost (value)) + x = riscv_split_integer (value, mode); + else +@@ -1357,7 +1368,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) + + for (i = 1; i < num_ops; i++) + { +- if (!can_create_pseudo_p ()) ++ if (!can_create_pseudo) + x = riscv_emit_set (temp, x); + else + x = force_reg (mode, x); +@@ -1381,12 +1392,12 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) + /* Split moves of big integers into smaller pieces. */ + if (splittable_const_int_operand (src, mode)) + { +- riscv_move_integer (dest, dest, INTVAL (src)); ++ riscv_move_integer (dest, dest, INTVAL (src), FALSE); + return; + } + + /* Split moves of symbolic constants into high/low pairs. */ +- if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) ++ if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE)) + { + riscv_emit_set (dest, src); + return; +@@ -1407,7 +1418,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) + if (offset != const0_rtx + && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) + { +- base = riscv_force_temporary (dest, base); ++ base = riscv_force_temporary (dest, base, FALSE); + riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); + return; + } +@@ -1416,7 +1427,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) + + /* When using explicit relocs, constant pool references are sometimes + not legitimate addresses. */ +- riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); ++ riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE); + riscv_emit_move (dest, src); + } + +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 7850c41f3c7e..e40535c9e405 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -1284,7 +1284,7 @@ + "" + [(const_int 0)] + { +- riscv_move_integer (operands[2], operands[0], INTVAL (operands[1])); ++ riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), TRUE); + DONE; + }) + +@@ -1293,11 +1293,11 @@ + [(set (match_operand:P 0 "register_operand") + (match_operand:P 1)) + (clobber (match_operand:P 2 "register_operand"))] +- "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" ++ "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)" + [(set (match_dup 0) (match_dup 3))] + { + riscv_split_symbol (operands[2], operands[1], +- MAX_MACHINE_MODE, &operands[3]); ++ MAX_MACHINE_MODE, &operands[3], TRUE); + }) + + ;; 64-bit integer moves diff --git a/gcc.spec b/gcc.spec index aebb820..5a33d07 100644 --- a/gcc.spec +++ b/gcc.spec @@ -101,7 +101,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: gcc Version: %{gcc_version} -Release: %{gcc_release}.0.riscv64%{?dist} +Release: %{gcc_release}.1.riscv64%{?dist} # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -249,6 +249,12 @@ Patch9: gcc9-Wno-format-security.patch Patch10: gcc9-rh1574936.patch Patch11: gcc9-d-shared-libphobos.patch +# RISC-V Backports (official, but not yet in Fedora) +# Patches taken from: +# https://github.com/gcc-mirror/gcc/commits/gcc-9-branch +Patch100: 6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch +Patch101: d6279ef7800d8d3c0cec208900e9c443af875bd1.patch + Patch1000: nvptx-tools-no-ptxas.patch Patch1001: nvptx-tools-build.patch Patch1002: nvptx-tools-glibc.patch @@ -765,6 +771,11 @@ to NVidia PTX capable devices if available. %endif %patch11 -p0 -b .d-shared-libphobos~ +%ifarch riscv64 +%patch100 -p1 -b .riscv64_1~ +%patch101 -p1 -b .riscv64_2~ +%endif + cd nvptx-tools-%{nvptx_tools_gitrev} %patch1000 -p1 -b .nvptx-tools-no-ptxas~ %patch1001 -p1 -b .nvptx-tools-build~