Remove obsolete RISC-V patches

These patches should be part of 0.16

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
This commit is contained in:
David Abdurachmanov 2019-05-01 18:42:01 +03:00
parent 6e5ee46df7
commit f51ed1b0d8
Signed by: davidlt
GPG Key ID: 7108702C938B13C1
3 changed files with 0 additions and 815 deletions

View File

@ -1,591 +0,0 @@
diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 72c43c69b..9452bd3a0 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -564,6 +564,10 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
if (subset_list->lookup ("d"))
*flags |= MASK_DOUBLE_FLOAT;
+ *flags &= ~MASK_RVC;
+ if (subset_list->lookup ("c"))
+ *flags |= MASK_RVC;
+
if (current_subset_list)
delete current_subset_list;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c
new file mode 100644
index 000000000..70f121f15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-1.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medlow" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if !defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if !defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-2.c b/gcc/testsuite/gcc.target/riscv/predef-2.c
new file mode 100644
index 000000000..6f3c8c386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-2.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32imaf -mabi=ilp32f -mcmodel=medany" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if !defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if !defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if !defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if !defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if !defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if !defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-3.c b/gcc/testsuite/gcc.target/riscv/predef-3.c
new file mode 100644
index 000000000..6f4f2e219
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-3.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32imafdc -mabi=ilp32d -fpic" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if !defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if !defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if !defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if !defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if !defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if !defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c
new file mode 100644
index 000000000..822f61782
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-4.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64ia -mabi=lp64 -mcmodel=medlow" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if !defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if !defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if !defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-5.c b/gcc/testsuite/gcc.target/riscv/predef-5.c
new file mode 100644
index 000000000..664904909
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-5.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64imf -mabi=lp64f -mcmodel=medany" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if !defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if !defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if !defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if !defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if !defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-6.c b/gcc/testsuite/gcc.target/riscv/predef-6.c
new file mode 100644
index 000000000..ee4e02bcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-6.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fpic" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if !defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if !defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if !defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if !defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if !defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if !defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c
new file mode 100644
index 000000000..0358f325c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-7.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if !defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if !defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if !defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if !defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-8.c b/gcc/testsuite/gcc.target/riscv/predef-8.c
new file mode 100644
index 000000000..41cd9feab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-8.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32if -mabi=ilp32f -mno-fdiv -mcmodel=medany" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if defined(__riscv_compressed)
+#error "__riscv_compressed"
+#endif
+
+#if defined(__riscv_32e)
+#error "__riscv_32e"
+#endif
+
+#if defined(__riscv_atomic)
+#error "__riscv_atomic"
+#endif
+
+#if defined(__riscv_mul)
+#error "__riscv_mul"
+#endif
+#if defined(__riscv_div)
+#error "__riscv_div"
+#endif
+#if defined(__riscv_muldiv)
+#error "__riscv_muldiv"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if defined(__riscv_fdiv)
+#error "__riscv_fdiv"
+#endif
+#if defined(__riscv_fsqrt)
+#error "__riscv_fsqrt"
+#endif
+
+#if defined(__riscv_abi_rve)
+#error "__riscv_abi_rve"
+#endif
+#if defined(__riscv_float_abi_soft)
+#error "__riscv_float_abi_soft"
+#endif
+#if !defined(__riscv_float_abi_single)
+#error "__riscv_float_abi_single"
+#endif
+#if defined(__riscv_float_abi_double)
+#error "__riscv_float_abi_double"
+#endif
+
+#if defined(__riscv_cmodel_medlow)
+#error "__riscv_cmodel_medlow"
+#endif
+#if !defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medlow"
+#endif
+#if defined(__riscv_cmodel_pic)
+#error "__riscv_cmodel_medlow"
+#endif
+
+ return 0;
+}

View File

@ -255,11 +255,6 @@ Patch9: gcc9-Wno-format-security.patch
Patch10: gcc9-rh1574936.patch
Patch11: gcc9-d-shared-libphobos.patch
Patch30: libphobos-enable-riscv-v3.patch
# Backport
# See: https://github.com/gcc-mirror/gcc/commit/f15d2aa02df3b06d07704584832ca023921e9ad2
Patch31: gcc-9.0.1-20190328-fix-riscv-compressed.patch
Patch1000: nvptx-tools-no-ptxas.patch
Patch1001: nvptx-tools-build.patch
Patch1002: nvptx-tools-glibc.patch
@ -770,9 +765,6 @@ to NVidia PTX capable devices if available.
%endif
%patch11 -p0 -b .d-shared-libphobos~
%patch30 -p1 -b .libphobos-riscv~
%patch31 -p1 -b .compressed-riscv~
cd nvptx-tools-%{nvptx_tools_gitrev}
%patch1000 -p1 -b .nvptx-tools-no-ptxas~
%patch1001 -p1 -b .nvptx-tools-build~

View File

@ -1,216 +0,0 @@
diff --git a/libphobos/configure.tgt b/libphobos/configure.tgt
index 0471bfd..811fdfa 100644
--- a/libphobos/configure.tgt
+++ b/libphobos/configure.tgt
@@ -32,6 +32,8 @@ case "${target}" in
;;
x86_64-*-netbsd* | i?86-*-netbsd*)
;;
+ riscv*-*-linux*)
+ ;;
*)
UNSUPPORTED=1
;;
diff --git a/libphobos/libdruntime/core/atomic.d b/libphobos/libdruntime/core/atomic.d
index 0b39cdd..5a6c4b8 100644
--- a/libphobos/libdruntime/core/atomic.d
+++ b/libphobos/libdruntime/core/atomic.d
@@ -1353,7 +1353,7 @@ else version (GNU)
private bool casImpl(T,V1,V2)( shared(T)* here, V1 ifThis, V2 writeThis ) pure nothrow @nogc @trusted
{
- static assert(GNU_Have_Atomics, "cas() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "cas() not supported on this architecture");
bool res = void;
static if (T.sizeof == byte.sizeof)
@@ -1406,7 +1406,7 @@ else version (GNU)
{
static assert(ms != MemoryOrder.rel, "Invalid MemoryOrder for atomicLoad");
static assert(__traits(isPOD, T), "argument to atomicLoad() must be POD");
- static assert(GNU_Have_Atomics, "atomicLoad() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "atomicLoad() not supported on this architecture");
static if (T.sizeof == ubyte.sizeof)
{
@@ -1444,7 +1444,7 @@ else version (GNU)
{
static assert(ms != MemoryOrder.acq, "Invalid MemoryOrder for atomicStore");
static assert(__traits(isPOD, T), "argument to atomicLoad() must be POD");
- static assert(GNU_Have_Atomics, "atomicStore() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "atomicStore() not supported on this architecture");
static if (T.sizeof == ubyte.sizeof)
{
diff --git a/libphobos/libdruntime/rt/sections_elf_shared.d b/libphobos/libdruntime/rt/sections_elf_shared.d
index d4e1ff0..45c1dcb 100644
--- a/libphobos/libdruntime/rt/sections_elf_shared.d
+++ b/libphobos/libdruntime/rt/sections_elf_shared.d
@@ -10,6 +10,9 @@
module rt.sections_elf_shared;
+version (RISCV32) version = RISCV_Any;
+version (RISCV64) version = RISCV_Any;
+
version (CRuntime_Glibc) enum SharedELF = true;
else version (FreeBSD) enum SharedELF = true;
else version (NetBSD) enum SharedELF = true;
@@ -671,7 +674,16 @@ version (Shared)
if (dyn.d_tag == DT_STRTAB)
{
version (linux)
- strtab = cast(const(char)*)dyn.d_un.d_ptr;
+ {
+ // This might change in future glibc releases (after 2.29) as dynamic sections
+ // are not required to be read-only on RISC-V. This was copy & pasted from MIPS while
+ // upstreaming RISC-V support. Otherwise MIPS is the only arch which sets in glibc:
+ // #define DL_RO_DYN_SECTION 1
+ version (RISCV_Any)
+ strtab = cast(const(char)*)(info.dlpi_addr + dyn.d_un.d_ptr); // relocate
+ else
+ strtab = cast(const(char)*)dyn.d_un.d_ptr;
+ }
else version (FreeBSD)
strtab = cast(const(char)*)(info.dlpi_addr + dyn.d_un.d_ptr); // relocate
else version (NetBSD)
diff --git a/libphobos/src/std/experimental/allocator/building_blocks/region.d b/libphobos/src/std/experimental/allocator/building_blocks/region.d
index dfcecce..cafe059 100644
--- a/libphobos/src/std/experimental/allocator/building_blocks/region.d
+++ b/libphobos/src/std/experimental/allocator/building_blocks/region.d
@@ -391,7 +391,8 @@ struct InSituRegion(size_t size, size_t minAlign = platformAlignment)
else version (PPC) enum growDownwards = Yes.growDownwards;
else version (PPC64) enum growDownwards = Yes.growDownwards;
else version (MIPS32) enum growDownwards = Yes.growDownwards;
- else version (MIPS64) enum growDownwards = Yes.growDownwards;
+ else version (RISCV32) enum growDownwards = Yes.growDownwards;
+ else version (RISCV64) enum growDownwards = Yes.growDownwards;
else version (SPARC) enum growDownwards = Yes.growDownwards;
else version (SystemZ) enum growDownwards = Yes.growDownwards;
else static assert(0, "Dunno how the stack grows on this architecture.");
diff --git a/libphobos/src/std/math.d b/libphobos/src/std/math.d
index e98e746..9fe7465 100644
--- a/libphobos/src/std/math.d
+++ b/libphobos/src/std/math.d
@@ -162,6 +162,8 @@ version (AArch64) version = ARM_Any;
version (ARM) version = ARM_Any;
version (SPARC) version = SPARC_Any;
version (SPARC64) version = SPARC_Any;
+version (RISCV32) version = RISCV_Any;
+version (RISCV64) version = RISCV_Any;
version (D_InlineAsm_X86)
{
@@ -4683,6 +4685,7 @@ private:
// The Pentium SSE2 status register is 32 bits.
// The ARM and PowerPC FPSCR is a 32-bit register.
// The SPARC FSR is a 32bit register (64 bits for SPARC 7 & 8, but high bits are uninteresting).
+ // The RISC-V (32 & 64 bit) fcsr is 32-bit register.
uint flags;
version (CRuntime_Microsoft)
@@ -4754,6 +4757,15 @@ private:
return result;
}
}
+ else version (RISCV_Any)
+ {
+ uint result = void;
+ asm pure nothrow @nogc
+ {
+ "frflags %0" : "=r" (result);
+ }
+ return result;
+ }
else
assert(0, "Not yet supported");
}
@@ -4828,6 +4840,14 @@ private:
}
}
}
+ else version (RISCV_Any)
+ {
+ uint newValues = 0x0;
+ asm pure nothrow @nogc
+ {
+ "fsflags %0" : : "r" (newValues);
+ }
+ }
else
assert(0, "Not yet supported");
}
@@ -4987,6 +5007,10 @@ else version (PPC_Any)
{
version = IeeeFlagsSupport;
}
+else version (RISCV_Any)
+{
+ version = IeeeFlagsSupport;
+}
else version (MIPS_Any)
{
version = IeeeFlagsSupport;
@@ -5226,6 +5250,21 @@ struct FloatingPointControl
| inexactException,
}
}
+ else version (RISCV_Any)
+ {
+ enum : ExceptionMask
+ {
+ inexactException = 0x01,
+ divByZeroException = 0x02,
+ underflowException = 0x04,
+ overflowException = 0x08,
+ invalidException = 0x10,
+ severeExceptions = overflowException | divByZeroException
+ | invalidException,
+ allExceptions = severeExceptions | underflowException
+ | inexactException,
+ }
+ }
else version (X86_Any)
{
enum : ExceptionMask
@@ -5338,6 +5377,10 @@ private:
{
alias ControlState = uint;
}
+ else version (RISCV_Any)
+ {
+ alias ControlState = uint;
+ }
else version (X86_Any)
{
alias ControlState = ushort;
@@ -5397,6 +5440,15 @@ private:
}
return cont;
}
+ else version (RISCV_Any)
+ {
+ ControlState cont;
+ asm pure nothrow @nogc
+ {
+ "frcsr %0" : "=r" (cont);
+ }
+ return cont;
+ }
else
assert(0, "Not yet supported");
}
@@ -5482,6 +5534,13 @@ private:
}
}
}
+ else version (RISCV_Any)
+ {
+ asm pure nothrow @nogc
+ {
+ "fscsr %0" : : "r" (newState);
+ }
+ }
else
assert(0, "Not yet supported");
}