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4.4.1-14

This commit is contained in:
Jakub Jelinek 2009-09-16 14:15:14 +00:00
parent d5843666e9
commit dad43f9003
6 changed files with 31 additions and 564 deletions
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2
.cvsignore
View File

@ -1,2 +1,2 @@
fastjar-0.97.tar.gz
gcc-4.4.1-20090911.tar.bz2
gcc-4.4.1-20090916.tar.bz2

2
gcc.spec
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@ -163,7 +163,6 @@ Patch19: gcc44-vta-cfgexpand-ptr-mode-pr41248.patch
Patch20: gcc44-powerpc-libgcc_s_so.patch
Patch21: gcc44-pr41175.patch
Patch22: gcc44-rh518303.patch
Patch23: gcc44-rh522577.patch
Patch1000: fastjar-0.97-segfault.patch
@ -473,7 +472,6 @@ which are required to compile with the GNAT.
%patch20 -p0 -b .powerpc-libgcc_s_so~
%patch21 -p0 -b .pr41175~
%patch22 -p0 -b .rh518303~
%patch23 -p0 -b .rh522577~
# This testcase doesn't compile.
rm libjava/testsuite/libjava.lang/PR35020*

516
gcc44-pr41175-2.patch
View File

@ -1,516 +0,0 @@
2009-09-11 Jakub Jelinek <jakub@redhat.com>
PR target/41175
* config/rs6000/rs6000.c (rs6000_emit_stack_reset): Handle savres
if sp_offset != 0 and frame_reg_rtx != sp_reg_rtx. Use gen_add3_insn
instead of gen_addsi3.
(rs6000_emit_epilogue): Set r11 from offsetted frame_reg_rtx instead
sp_reg_rtx, if frame_reg_rtx is r11, adjust sp_offset. Use
gen_add3_insn instead of gen_addsi3. Merge two adjacent ifs with the
same condition.
* gcc.target/powerpc/pr41175.c: New test.
--- gcc/config/rs6000/rs6000.c.jj 2009-09-09 20:46:57.000000000 +0200
+++ gcc/config/rs6000/rs6000.c 2009-09-11 10:29:01.101406443 +0200
@@ -18083,8 +18083,12 @@ rs6000_emit_stack_reset (rs6000_stack_t
{
rs6000_emit_stack_tie ();
if (sp_offset != 0)
- return emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
- GEN_INT (sp_offset)));
+ {
+ rtx dest_reg = savres ? gen_rtx_REG (Pmode, 11) : sp_reg_rtx;
+
+ return emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx,
+ GEN_INT (sp_offset)));
+ }
else if (!savres)
return emit_move_insn (sp_reg_rtx, frame_reg_rtx);
}
@@ -19525,9 +19529,13 @@ rs6000_emit_epilogue (int sibcall)
rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
sp_offset, can_use_exit);
else
- emit_insn (gen_addsi3 (gen_rtx_REG (Pmode, 11),
- sp_reg_rtx,
- GEN_INT (sp_offset - info->fp_size)));
+ {
+ emit_insn (gen_add3_insn (gen_rtx_REG (Pmode, 11),
+ frame_reg_rtx,
+ GEN_INT (sp_offset - info->fp_size)));
+ if (REGNO (frame_reg_rtx) == 11)
+ sp_offset += info->fp_size;
+ }
par = rs6000_make_savres_rtx (info, frame_reg_rtx,
info->gp_save_offset, reg_mode,
@@ -19632,12 +19640,10 @@ rs6000_emit_epilogue (int sibcall)
info->lr_save_offset + sp_offset);
emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
+ emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
+ gen_rtx_REG (Pmode, 0));
}
- if (restore_lr && !restoring_GPRs_inline)
- emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
- gen_rtx_REG (Pmode, 0));
-
/* Restore fpr's if we need to do it without calling a function. */
if (restoring_FPRs_inline)
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
--- gcc/testsuite/gcc.target/powerpc/pr41175.c.jj 2009-09-11 10:28:50.529527601 +0200
+++ gcc/testsuite/gcc.target/powerpc/pr41175.c 2009-09-11 10:18:59.000000000 +0200
@@ -0,0 +1,451 @@
+/* PR target/41175 */
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+
+#define X2(n) X1(n##0) X1(n##1)
+#define X4(n) X2(n##0) X2(n##1)
+#define X8(n) X4(n##0) X4(n##1)
+
+volatile int ll;
+
+__attribute__((noinline)) void
+foo (void)
+{
+ asm volatile ("" : : : "memory");
+}
+
+__attribute__((noinline)) void
+bar (char *p)
+{
+ asm volatile ("" : : "r" (p) : "memory");
+}
+
+__attribute__((noinline)) void
+f1 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+ foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f2 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+ char *pp = __builtin_alloca (ll);
+ bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f3 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f4 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+ foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f5 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+ char *pp = __builtin_alloca (ll);
+ bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f6 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f7 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+ foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f8 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+ char *pp = __builtin_alloca (ll);
+ bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f9 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f10 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+ foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f11 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+ char *pp = __builtin_alloca (ll);
+ bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f12 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f13 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+ foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f14 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+ char *pp = __builtin_alloca (ll);
+ bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f15 (void)
+{
+ int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+ X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+ X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+ asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+ asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+ asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+f" (fpr##n),
+ asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+ asm volatile ("" : : X8(a) "m" (mem) : "memory");
+ asm volatile ("" : : X8(b) "m" (mem) : "memory");
+ asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) "f" (fpr##n),
+ asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+
+int
+main ()
+{
+ ll = 60;
+ f1 ();
+ f2 ();
+ f3 ();
+ f4 ();
+ f5 ();
+ f6 ();
+ f7 ();
+ f8 ();
+ f9 ();
+ f10 ();
+ f11 ();
+ f12 ();
+ f13 ();
+ f14 ();
+ f15 ();
+ return 0;
+}

58
gcc44-pr41175.patch
View File

@ -571,7 +571,7 @@
#undef PREFERRED_DEBUGGING_TYPE
--- gcc/config/rs6000/rs6000.c (revision 151728)
+++ gcc/config/rs6000/rs6000.c (revision 151729)
@@ -18033,7 +18033,8 @@ static bool
@@ -17980,7 +17980,8 @@ static bool
no_global_regs_above (int first, bool gpr)
{
int i;
@ -581,7 +581,7 @@
if (global_regs[i])
return false;
return true;
@@ -18050,54 +18051,136 @@ no_global_regs_above (int first, bool gp
@@ -17997,54 +17998,136 @@ no_global_regs_above (int first, bool gp
static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
@ -748,9 +748,9 @@
}
return sym;
@@ -18124,8 +18207,11 @@ rs6000_emit_stack_reset (rs6000_stack_t
if (frame_reg_rtx != sp_reg_rtx)
@@ -18072,8 +18155,11 @@ rs6000_emit_stack_reset (rs6000_stack_t
{
rs6000_emit_stack_tie ();
if (sp_offset != 0)
- return emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
- GEN_INT (sp_offset)));
@ -762,7 +762,7 @@
else if (!savres)
return emit_move_insn (sp_reg_rtx, frame_reg_rtx);
}
@@ -18154,7 +18240,7 @@ static rtx
@@ -18102,7 +18188,7 @@ static rtx
rs6000_make_savres_rtx (rs6000_stack_t *info,
rtx frame_reg_rtx, int save_area_offset,
enum machine_mode reg_mode,
@ -771,7 +771,7 @@
{
int i;
int offset, start_reg, end_reg, n_regs;
@@ -18168,20 +18254,21 @@ rs6000_make_savres_rtx (rs6000_stack_t *
@@ -18116,20 +18202,21 @@ rs6000_make_savres_rtx (rs6000_stack_t *
: info->first_fp_reg_save);
end_reg = gpr ? 32 : 64;
n_regs = end_reg - start_reg;
@ -800,7 +800,7 @@
for (i = 0; i < end_reg - start_reg; i++)
{
@@ -18196,6 +18283,16 @@ rs6000_make_savres_rtx (rs6000_stack_t *
@@ -18144,6 +18231,16 @@ rs6000_make_savres_rtx (rs6000_stack_t *
savep ? reg : mem);
}
@ -817,7 +817,7 @@
return gen_rtx_PARALLEL (VOIDmode, p);
}
@@ -18216,7 +18313,10 @@ rs6000_reg_live_or_pic_offset_p (int reg
@@ -18164,7 +18261,10 @@ rs6000_reg_live_or_pic_offset_p (int reg
enum {
SAVRES_MULTIPLE = 0x1,
SAVRES_INLINE_FPRS = 0x2,
@ -829,7 +829,7 @@
};
/* Determine the strategy for savings/restoring registers. */
@@ -18231,6 +18331,7 @@ rs6000_savres_strategy (rs6000_stack_t *
@@ -18179,6 +18279,7 @@ rs6000_savres_strategy (rs6000_stack_t *
bool savres_gprs_inline;
bool noclobber_global_gprs
= no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true);
@ -837,7 +837,7 @@
using_multiple_p = (TARGET_MULTIPLE && ! TARGET_POWERPC64
&& (!TARGET_SPE_ABI
@@ -18250,6 +18351,10 @@ rs6000_savres_strategy (rs6000_stack_t *
@@ -18198,6 +18299,10 @@ rs6000_savres_strategy (rs6000_stack_t *
|| info->first_fp_reg_save == 64
|| !no_global_regs_above (info->first_fp_reg_save,
/*gpr=*/false)
@ -848,7 +848,7 @@
|| FP_SAVE_INLINE (info->first_fp_reg_save));
savres_gprs_inline = (common
/* Saving CR interferes with the exit routines
@@ -18287,9 +18392,22 @@ rs6000_savres_strategy (rs6000_stack_t *
@@ -18235,9 +18340,22 @@ rs6000_savres_strategy (rs6000_stack_t *
savres_gprs_inline = savres_gprs_inline || using_multiple_p;
}
@ -874,7 +874,7 @@
}
/* Emit function prologue as insns. */
@@ -18311,7 +18429,7 @@ rs6000_emit_prologue (void)
@@ -18259,7 +18377,7 @@ rs6000_emit_prologue (void)
int using_store_multiple;
int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
&& df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
@ -883,7 +883,7 @@
HOST_WIDE_INT sp_offset = 0;
if (TARGET_FIX_AND_CONTINUE)
@@ -18496,24 +18614,30 @@ rs6000_emit_prologue (void)
@@ -18444,24 +18562,30 @@ rs6000_emit_prologue (void)
gen_rtx_REG (Pmode, LR_REGNO));
RTX_FRAME_RELATED_P (insn) = 1;
@ -924,7 +924,7 @@
insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
RTX_FRAME_RELATED_P (insn) = 1;
/* Now, there's no way that dwarf2out_frame_debug_expr is going
@@ -18550,7 +18674,9 @@ rs6000_emit_prologue (void)
@@ -18500,7 +18624,9 @@ rs6000_emit_prologue (void)
info->fp_save_offset + sp_offset,
DFmode,
/*savep=*/true, /*gpr=*/false,
@ -935,7 +935,7 @@
insn = emit_insn (par);
rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
NULL_RTX, NULL_RTX);
@@ -18646,7 +18772,7 @@ rs6000_emit_prologue (void)
@@ -18596,7 +18722,7 @@ rs6000_emit_prologue (void)
par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
0, reg_mode,
/*savep=*/true, /*gpr=*/true,
@ -944,7 +944,7 @@
insn = emit_insn (par);
rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
NULL_RTX, NULL_RTX);
@@ -18661,23 +18787,23 @@ rs6000_emit_prologue (void)
@@ -18611,23 +18737,23 @@ rs6000_emit_prologue (void)
{
rtx par;
@ -976,7 +976,7 @@
insn = emit_insn (par);
rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
NULL_RTX, NULL_RTX);
@@ -18954,9 +19080,18 @@ rs6000_output_function_prologue (FILE *f
@@ -18907,9 +19033,18 @@ rs6000_output_function_prologue (FILE *f
fp values. */
if (info->first_fp_reg_save < 64
&& !FP_SAVE_INLINE (info->first_fp_reg_save))
@ -998,7 +998,7 @@
/* Write .extern for AIX common mode routines, if needed. */
if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
@@ -19082,6 +19217,7 @@ rs6000_emit_epilogue (int sibcall)
@@ -19035,6 +19170,7 @@ rs6000_emit_epilogue (int sibcall)
rtx frame_reg_rtx = sp_reg_rtx;
rtx cfa_restores = NULL_RTX;
rtx insn;
@ -1006,7 +1006,7 @@
enum machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
int i;
@@ -19115,8 +19251,10 @@ rs6000_emit_epilogue (int sibcall)
@@ -19068,8 +19204,10 @@ rs6000_emit_epilogue (int sibcall)
|| (cfun->calls_alloca
&& !frame_pointer_needed));
restore_lr = (info->lr_save_p
@ -1019,7 +1019,7 @@
if (WORLD_SAVE_P (info))
{
@@ -19403,7 +19541,7 @@ rs6000_emit_epilogue (int sibcall)
@@ -19356,7 +19494,7 @@ rs6000_emit_epilogue (int sibcall)
/* Get the old lr if we saved it. If we are restoring registers
out-of-line, then the out-of-line routines can do this for us. */
@ -1028,7 +1028,7 @@
{
rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
info->lr_save_offset + sp_offset);
@@ -19418,12 +19556,17 @@ rs6000_emit_epilogue (int sibcall)
@@ -19371,12 +19509,17 @@ rs6000_emit_epilogue (int sibcall)
GEN_INT (info->cr_save_offset + sp_offset));
rtx mem = gen_frame_mem (SImode, addr);
@ -1048,7 +1048,7 @@
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
gen_rtx_REG (Pmode, 0));
@@ -19540,7 +19683,7 @@ rs6000_emit_epilogue (int sibcall)
@@ -19493,7 +19636,7 @@ rs6000_emit_epilogue (int sibcall)
par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
0, reg_mode,
/*savep=*/false, /*gpr=*/true,
@ -1057,7 +1057,7 @@
emit_jump_insn (par);
/* We don't want anybody else emitting things after we jumped
back. */
@@ -19558,21 +19701,25 @@ rs6000_emit_epilogue (int sibcall)
@@ -19511,21 +19654,25 @@ rs6000_emit_epilogue (int sibcall)
rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
sp_offset, can_use_exit);
else
@ -1088,8 +1088,8 @@
+ rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
if (DEFAULT_ABI == ABI_V4)
cfa_restores
= alloc_reg_note (REG_CFA_RESTORE,
@@ -19659,6 +19806,16 @@ rs6000_emit_epilogue (int sibcall)
= alloc_EXPR_LIST (REG_CFA_RESTORE,
@@ -19612,6 +19759,16 @@ rs6000_emit_epilogue (int sibcall)
}
}
@ -1106,7 +1106,7 @@
/* Restore fpr's if we need to do it without calling a function. */
if (restoring_FPRs_inline)
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
@@ -19685,7 +19842,7 @@ rs6000_emit_epilogue (int sibcall)
@@ -19638,7 +19795,7 @@ rs6000_emit_epilogue (int sibcall)
/* If we saved cr, restore it here. Just those that were used. */
if (info->cr_save_p)
{
@ -1114,8 +1114,8 @@
+ rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
if (DEFAULT_ABI == ABI_V4)
cfa_restores
= alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (SImode, CR2_REGNO),
@@ -19716,13 +19873,14 @@ rs6000_emit_epilogue (int sibcall)
= alloc_EXPR_LIST (REG_CFA_RESTORE, gen_rtx_REG (SImode, CR2_REGNO),
@@ -19669,13 +19826,14 @@ rs6000_emit_epilogue (int sibcall)
if (!sibcall)
{
rtvec p;
@ -1131,7 +1131,7 @@
? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
: gen_rtx_CLOBBER (VOIDmode,
gen_rtx_REG (Pmode, 65)));
@@ -19737,10 +19895,12 @@ rs6000_emit_epilogue (int sibcall)
@@ -19690,10 +19848,12 @@ rs6000_emit_epilogue (int sibcall)
sym = rs6000_savres_routine_sym (info,
/*savep=*/false,
/*gpr=*/false,

15
gcc44-rh522577.patch
View File

@ -1,15 +0,0 @@
2009-09-11 Jakub Jelinek <jakub@redhat.com>
* combine.c (propagate_for_debug_subst): Call wrap_constant on top.
--- gcc/combine.c.jj 2009-09-08 12:32:31.000000000 +0200
+++ gcc/combine.c 2009-09-11 11:01:32.000000000 +0200
@@ -2311,7 +2311,7 @@ propagate_for_debug_subst (rtx *loc, voi
to = simplify_gen_subreg (GET_MODE (x), to,
GET_MODE (from), SUBREG_BYTE (x));
}
- *loc = to;
+ *loc = wrap_constant (GET_MODE (x), to);
pair->changed = true;
return -1;
}

2
sources
View File

@ -1,2 +1,2 @@
2659f09c2e43ef8b7d4406321753f1b2 fastjar-0.97.tar.gz
36739b78d9654be37ccf6019e72db459 gcc-4.4.1-20090911.tar.bz2
921813722475a64597078d02577eda9c gcc-4.4.1-20090916.tar.bz2