diff --git a/0180b20de73778fe1e67060f66c7f47630aeb949.patch b/0180b20de73778fe1e67060f66c7f47630aeb949.patch new file mode 100644 index 0000000..1c91cb5 --- /dev/null +++ b/0180b20de73778fe1e67060f66c7f47630aeb949.patch @@ -0,0 +1,49 @@ +From 0180b20de73778fe1e67060f66c7f47630aeb949 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:46:37 -0700 +Subject: [PATCH] RISC-V: Enforce atomic compare_exchange SEQ_CST + +This patch enforces SEQ_CST for atomic compare_exchange ops. + +Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs +recommended by table A.6 of the ISA manual. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/sync.md (atomic_cas_value_strong): Change + FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl + pair. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 0c83ef046070..5620d6ffa587 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -297,9 +297,16 @@ + UNSPEC_COMPARE_AND_SWAP)) + (clobber (match_scratch:GPR 6 "=&r"))] + "TARGET_ATOMIC" +- "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" ++ { ++ return "1:\;" ++ "lr..aqrl\t%0,%1\;" ++ "bne\t%0,%z2,1f\;" ++ "sc..rl\t%6,%z3,%1\;" ++ "bnez\t%6,1b\;" ++ "1:"; ++ } + [(set_attr "type" "atomic") +- (set (attr "length") (const_int 20))]) ++ (set (attr "length") (const_int 16))]) + + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand" "") ;; bool output +-- +2.39.3 + diff --git a/0e42ac31fdeffdcec22f1935534693d4cef62e0b.patch b/0e42ac31fdeffdcec22f1935534693d4cef62e0b.patch new file mode 100644 index 0000000..94f4d5f --- /dev/null +++ b/0e42ac31fdeffdcec22f1935534693d4cef62e0b.patch @@ -0,0 +1,69 @@ +From 0e42ac31fdeffdcec22f1935534693d4cef62e0b Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Fri, 7 Apr 2023 15:14:17 -0700 +Subject: [PATCH] RISC-V: Weaken atomic loads + +This change brings atomic loads in line with table A.6 of the ISA +manual. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/sync.md (atomic_load): Implement atomic + load mapping. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++-- + 1 file changed, 26 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index ba132d8a1cea..6e7c762ac577 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -26,6 +26,7 @@ + UNSPEC_SYNC_OLD_OP_SUBWORD + UNSPEC_SYNC_EXCHANGE + UNSPEC_SYNC_EXCHANGE_SUBWORD ++ UNSPEC_ATOMIC_LOAD + UNSPEC_ATOMIC_STORE + UNSPEC_MEMORY_BARRIER + ]) +@@ -66,8 +67,31 @@ + + ;; Atomic memory operations. + +-;; Implement atomic stores with conservative fences. Fall back to fences for +-;; atomic loads. ++(define_insn "atomic_load" ++ [(set (match_operand:GPR 0 "register_operand" "=r") ++ (unspec_volatile:GPR ++ [(match_operand:GPR 1 "memory_operand" "A") ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPEC_ATOMIC_LOAD))] ++ "TARGET_ATOMIC" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ model = memmodel_base (model); ++ ++ if (model == MEMMODEL_SEQ_CST) ++ return "fence\trw,rw\;" ++ "l\t%0,%1\;" ++ "fence\tr,rw"; ++ if (model == MEMMODEL_ACQUIRE) ++ return "l\t%0,%1\;" ++ "fence\tr,rw"; ++ else ++ return "l\t%0,%1"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 12))]) ++ ++;; Implement atomic stores with conservative fences. + ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. + (define_insn "atomic_store" + [(set (match_operand:GPR 0 "memory_operand" "=A") +-- +2.39.3 + diff --git a/1e9180b3298def6c01d9055d558fdb52231f8d2d.patch b/1e9180b3298def6c01d9055d558fdb52231f8d2d.patch new file mode 100644 index 0000000..202eaca --- /dev/null +++ b/1e9180b3298def6c01d9055d558fdb52231f8d2d.patch @@ -0,0 +1,35 @@ +From 1e9180b3298def6c01d9055d558fdb52231f8d2d Mon Sep 17 00:00:00 2001 +From: Martin Liska +Date: Wed, 3 May 2023 16:35:26 +0200 +Subject: [PATCH] riscv: fix error: control reaches end of non-void function + +Fixes: +gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void function [-Werror=return-type] +66 | [(set (attr "length") (const_int 4))]) + | ^ + + PR target/109713 + +gcc/ChangeLog: + + * config/riscv/sync.md: Add gcc_unreachable to a switch. +--- + gcc/config/riscv/sync.md | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 6e7c762ac577..9fc626267de3 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -62,6 +62,8 @@ + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; ++ else ++ gcc_unreachable (); + } + [(set (attr "length") (const_int 4))]) + +-- +2.39.3 + diff --git a/36a84e538bb9d3feb1762200074f39a1e9ff4fce.patch b/36a84e538bb9d3feb1762200074f39a1e9ff4fce.patch new file mode 100644 index 0000000..1db7c4e --- /dev/null +++ b/36a84e538bb9d3feb1762200074f39a1e9ff4fce.patch @@ -0,0 +1,57 @@ +From 36a84e538bb9d3feb1762200074f39a1e9ff4fce Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Fri, 7 Apr 2023 10:44:09 -0700 +Subject: [PATCH] RISC-V: Weaken mem_thread_fence + +This change brings atomic fences in line with table A.6 of the ISA +manual. + +Relax mem_thread_fence according to the memmodel given. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/sync.md (mem_thread_fence_1): Change fence + depending on the given memory model. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 3e6345e83a35..ba132d8a1cea 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -45,14 +45,24 @@ + DONE; + }) + +-;; Until the RISC-V memory model (hence its mapping from C++) is finalized, +-;; conservatively emit a full FENCE. + (define_insn "mem_thread_fence_1" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) + (match_operand:SI 1 "const_int_operand" "")] ;; model + "" +- "fence\tiorw,iorw") ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[1]); ++ model = memmodel_base (model); ++ if (model == MEMMODEL_SEQ_CST) ++ return "fence\trw,rw"; ++ else if (model == MEMMODEL_ACQ_REL) ++ return "fence.tso"; ++ else if (model == MEMMODEL_ACQUIRE) ++ return "fence\tr,rw"; ++ else if (model == MEMMODEL_RELEASE) ++ return "fence\trw,w"; ++ } ++ [(set (attr "length") (const_int 4))]) + + ;; Atomic memory operations. + +-- +2.39.3 + diff --git a/444d909b323d94639e60aab6c4089ff839c0f0e9.patch b/444d909b323d94639e60aab6c4089ff839c0f0e9.patch new file mode 100644 index 0000000..c2354af --- /dev/null +++ b/444d909b323d94639e60aab6c4089ff839c0f0e9.patch @@ -0,0 +1,632 @@ +From 444d909b323d94639e60aab6c4089ff839c0f0e9 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Fri, 7 Apr 2023 13:13:21 -0700 +Subject: [PATCH] RISC-V: Table A.6 conformance tests + +These tests cover basic cases to ensure the atomic mappings follow the +strengthened Table A.6 mappings that are compatible with Table A.7. + +2023-04-27 Patrick O'Neill + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-1.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-2.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-3.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-4.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-5.c: New test. + * gcc.target/riscv/amo-table-a-6-load-1.c: New test. + * gcc.target/riscv/amo-table-a-6-load-2.c: New test. + * gcc.target/riscv/amo-table-a-6-load-3.c: New test. + * gcc.target/riscv/amo-table-a-6-store-1.c: New test. + * gcc.target/riscv/amo-table-a-6-store-2.c: New test. + * gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test. + +Signed-off-by: Patrick O'Neill +--- + .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 15 +++++++++++++++ + .../riscv/amo-table-a-6-compare-exchange-1.c | 9 +++++++++ + .../riscv/amo-table-a-6-compare-exchange-2.c | 9 +++++++++ + .../riscv/amo-table-a-6-compare-exchange-3.c | 9 +++++++++ + .../riscv/amo-table-a-6-compare-exchange-4.c | 9 +++++++++ + .../riscv/amo-table-a-6-compare-exchange-5.c | 9 +++++++++ + .../riscv/amo-table-a-6-compare-exchange-6.c | 10 ++++++++++ + .../riscv/amo-table-a-6-compare-exchange-7.c | 9 +++++++++ + .../gcc.target/riscv/amo-table-a-6-fence-1.c | 14 ++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-fence-2.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-fence-3.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-fence-4.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-fence-5.c | 15 +++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-load-1.c | 16 ++++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-load-2.c | 17 +++++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-load-3.c | 18 ++++++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-store-1.c | 16 ++++++++++++++++ + .../gcc.target/riscv/amo-table-a-6-store-2.c | 17 +++++++++++++++++ + .../riscv/amo-table-a-6-store-compat-3.c | 18 ++++++++++++++++++ + .../riscv/amo-table-a-6-subword-amo-add-1.c | 9 +++++++++ + .../riscv/amo-table-a-6-subword-amo-add-2.c | 9 +++++++++ + .../riscv/amo-table-a-6-subword-amo-add-3.c | 9 +++++++++ + .../riscv/amo-table-a-6-subword-amo-add-4.c | 9 +++++++++ + .../riscv/amo-table-a-6-subword-amo-add-5.c | 9 +++++++++ + 28 files changed, 360 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +new file mode 100644 +index 000000000000..071a33928fe9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +new file mode 100644 +index 000000000000..d6b2d91db2ab +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\.aq\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +new file mode 100644 +index 000000000000..68a69ed8b780 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\.rl\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +new file mode 100644 +index 000000000000..b5cac4c47970 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +new file mode 100644 +index 000000000000..268e58cb95f0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +new file mode 100644 +index 000000000000..8349e7a69ac2 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +new file mode 100644 +index 000000000000..bf30b298b4b5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +new file mode 100644 +index 000000000000..41444ec95e90 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +new file mode 100644 +index 000000000000..dc2d7bd300d3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +new file mode 100644 +index 000000000000..53246210900c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +new file mode 100644 +index 000000000000..1376ac2a95bb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Mixed mappings need to be unioned. */ ++/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +new file mode 100644 +index 000000000000..98083cbae083 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (int bar, int baz, int qux) ++{ ++ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c +new file mode 100644 +index 000000000000..bf590489c398 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** ret ++*/ ++void foo() ++{ ++ __atomic_thread_fence(__ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c +new file mode 100644 +index 000000000000..9848f8cae31a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** fence\tr,rw ++** ret ++*/ ++void foo() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c +new file mode 100644 +index 000000000000..3c3ce6e0d182 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** fence\trw,w ++** ret ++*/ ++void foo() ++{ ++ __atomic_thread_fence(__ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c +new file mode 100644 +index 000000000000..12d717170858 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** fence\.tso ++** ret ++*/ ++void foo() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQ_REL); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c +new file mode 100644 +index 000000000000..9567b604c2c9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** fence\trw,rw ++** ret ++*/ ++void foo() ++{ ++ __atomic_thread_fence(__ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c +new file mode 100644 +index 000000000000..3c79035e46d6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** lw\ta[0-9]+,0\(a0\) ++** sw\ta[0-9]+,0\(a1\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c +new file mode 100644 +index 000000000000..7d74841846fa +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** lw\ta[0-9]+,0\(a0\) ++** fence\tr,rw ++** sw\ta[0-9]+,0\(a1\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c +new file mode 100644 +index 000000000000..ab95fa660d25 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** fence\trw,rw ++** lw\ta[0-9]+,0\(a0\) ++** fence\tr,rw ++** sw\ta[0-9]+,0\(a1\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c +new file mode 100644 +index 000000000000..d852fddf03de +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* Verify that store mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** lw\ta[0-9]+,0\(a1\) ++** sw\ta[0-9]+,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c +new file mode 100644 +index 000000000000..ccb5e2af7cc1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Verify that store mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** lw\ta[0-9]+,0\(a1\) ++** fence\trw,w ++** sw\ta[0-9]+,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c +new file mode 100644 +index 000000000000..761889f18cf9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* Verify that store mapping are compatible with Table A.6 & A.7. */ ++/* { dg-options "-O3" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** lw\ta[0-9]+,0\(a1\) ++** fence\trw,w ++** sw\ta[0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +new file mode 100644 +index 000000000000..d7d887dd1814 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ ++ ++void foo (short* bar, short* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +new file mode 100644 +index 000000000000..897bad26ebdf +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ ++ ++void foo (short* bar, short* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +new file mode 100644 +index 000000000000..79efca2839a8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (short* bar, short* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +new file mode 100644 +index 000000000000..772ac1be6ebc +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (short* bar, short* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +new file mode 100644 +index 000000000000..b0bec66990e0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ ++/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ ++ ++void foo (short* bar, short* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +-- +2.39.3 + diff --git a/4b6751b6a1fd054b33a57cfb942fb895b624f3e8.patch b/4b6751b6a1fd054b33a57cfb942fb895b624f3e8.patch new file mode 100644 index 0000000..b9c1264 --- /dev/null +++ b/4b6751b6a1fd054b33a57cfb942fb895b624f3e8.patch @@ -0,0 +1,45 @@ +From 4b6751b6a1fd054b33a57cfb942fb895b624f3e8 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:44:57 -0700 +Subject: [PATCH] RISC-V: Enforce Libatomic LR/SC SEQ_CST + +Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs +recommended by table A.6 of the ISA manual. + +2023-04-27 Patrick O'Neill + +libgcc/ChangeLog: + + * config/riscv/atomic.c: Change LR.aq/SC.rl pairs into + sequentially consistent LR.aqrl/SC.rl pairs. + +Signed-off-by: Patrick O'Neill +--- + libgcc/config/riscv/atomic.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c +index 573d163ea049..bd2b033132ba 100644 +--- a/libgcc/config/riscv/atomic.c ++++ b/libgcc/config/riscv/atomic.c +@@ -41,7 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + unsigned old, tmp1, tmp2; \ + \ + asm volatile ("1:\n\t" \ +- "lr.w.aq %[old], %[mem]\n\t" \ ++ "lr.w.aqrl %[old], %[mem]\n\t" \ + #insn " %[tmp1], %[old], %[value]\n\t" \ + invert \ + "and %[tmp1], %[tmp1], %[mask]\n\t" \ +@@ -75,7 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + unsigned old, tmp1; \ + \ + asm volatile ("1:\n\t" \ +- "lr.w.aq %[old], %[mem]\n\t" \ ++ "lr.w.aqrl %[old], %[mem]\n\t" \ + "and %[tmp1], %[old], %[mask]\n\t" \ + "bne %[tmp1], %[o], 1f\n\t" \ + "and %[tmp1], %[old], %[not_mask]\n\t" \ +-- +2.39.3 + diff --git a/687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6.patch b/687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6.patch new file mode 100644 index 0000000..ac98cfc --- /dev/null +++ b/687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6.patch @@ -0,0 +1,41 @@ +From 687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:47:05 -0700 +Subject: [PATCH] RISC-V: Add AMO release bits + +This patch sets the relevant .rl bits on amo operations. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_print_operand): Change behavior + of %A to include release bits. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/riscv.cc | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 11b897aca5c4..df55c427b1b3 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) + break; + + case 'A': +- if (riscv_memmodel_needs_amo_acquire (model)) ++ if (riscv_memmodel_needs_amo_acquire (model) ++ && riscv_memmodel_needs_release_fence (model)) ++ fputs (".aqrl", file); ++ else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); ++ else if (riscv_memmodel_needs_release_fence (model)) ++ fputs (".rl", file); + break; + + case 'F': +-- +2.39.3 + diff --git a/71506544eef580f59e5816f0a48a67aebbe5eed5.patch b/71506544eef580f59e5816f0a48a67aebbe5eed5.patch new file mode 100644 index 0000000..3ee4022 --- /dev/null +++ b/71506544eef580f59e5816f0a48a67aebbe5eed5.patch @@ -0,0 +1,349 @@ +From 71506544eef580f59e5816f0a48a67aebbe5eed5 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:49:20 -0700 +Subject: [PATCH] RISC-V: Weaken LR/SC pairs + +Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs +as needed. + +Atomic compare and exchange ops provide success and failure memory +models. C++17 and later place no restrictions on the relative strength +of each model, so ensure we cover both by using a model that enforces +the ordering of both given models. + +This change brings LR/SC ops in line with table A.6 of the ISA manual. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose + riscv_union_memmodels function to sync.md. + * config/riscv/riscv.cc (riscv_union_memmodels): Add function to + get the union of two memmodels in sync.md. + (riscv_print_operand): Add %I and %J flags that output the + optimal LR/SC flag bits for a given memory model. + * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl + bits on SC op and replace with optimized %I, %J flags. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/riscv-protos.h | 3 + + gcc/config/riscv/riscv.cc | 44 ++++++++++++ + gcc/config/riscv/sync.md | 114 +++++++++++++++++++------------- + 3 files changed, 114 insertions(+), 47 deletions(-) + +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index 02b33e020207..b5616fb3e88c 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see + #ifndef GCC_RISCV_PROTOS_H + #define GCC_RISCV_PROTOS_H + ++#include "memmodel.h" ++ + /* Symbol types we understand. The order of this list must match that of + the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ + enum riscv_symbol_type { +@@ -81,6 +83,7 @@ extern bool riscv_v_ext_vector_mode_p (machine_mode); + extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); + extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); + extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); ++extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); + + /* Routines implemented in riscv-c.cc. */ + void riscv_cpu_cpp_builtins (cpp_reader *); +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 951f6b5cf42d..59899268918d 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -4284,6 +4284,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) + fputc (')', file); + } + ++/* Return the memory model that encapuslates both given models. */ ++ ++enum memmodel ++riscv_union_memmodels (enum memmodel model1, enum memmodel model2) ++{ ++ model1 = memmodel_base (model1); ++ model2 = memmodel_base (model2); ++ ++ enum memmodel weaker = model1 <= model2 ? model1: model2; ++ enum memmodel stronger = model1 > model2 ? model1: model2; ++ ++ switch (stronger) ++ { ++ case MEMMODEL_SEQ_CST: ++ case MEMMODEL_ACQ_REL: ++ return stronger; ++ case MEMMODEL_RELEASE: ++ if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) ++ return MEMMODEL_ACQ_REL; ++ else ++ return stronger; ++ case MEMMODEL_ACQUIRE: ++ case MEMMODEL_CONSUME: ++ case MEMMODEL_RELAXED: ++ return stronger; ++ default: ++ gcc_unreachable (); ++ } ++} ++ + /* Return true if the .AQ suffix should be added to an AMO to implement the + acquire portion of memory model MODEL. */ + +@@ -4337,6 +4367,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) + 'R' Print the low-part relocation associated with OP. + 'C' Print the integer branch condition for comparison OP. + 'A' Print the atomic operation suffix for memory model OP. ++ 'I' Print the LR suffix for memory model OP. ++ 'J' Print the SC suffix for memory model OP. + 'z' Print x0 if OP is zero, otherwise print OP normally. + 'i' Print i if the operand is not a register. + 'S' Print shift-index of single-bit mask OP. +@@ -4506,6 +4538,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) + fputs (".rl", file); + break; + ++ case 'I': ++ if (model == MEMMODEL_SEQ_CST) ++ fputs (".aqrl", file); ++ else if (riscv_memmodel_needs_amo_acquire (model)) ++ fputs (".aq", file); ++ break; ++ ++ case 'J': ++ if (riscv_memmodel_needs_amo_release (model)) ++ fputs (".rl", file); ++ break; ++ + case 'i': + if (code != REG) + fputs ("i", file); +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 9a3b57bd09fd..3e6345e83a35 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -116,21 +116,22 @@ + (unspec_volatile:SI + [(any_atomic:SI (match_dup 1) + (match_operand:SI 2 "register_operand" "rI")) ;; value for op +- (match_operand:SI 3 "register_operand" "rI")] ;; mask ++ (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP_SUBWORD)) +- (match_operand:SI 4 "register_operand" "rI") ;; not_mask +- (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 +- (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 ++ (match_operand:SI 4 "register_operand" "rI") ;; mask ++ (match_operand:SI 5 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 ++ (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aqrl\t%0, %1\;" +- "\t%5, %0, %2\;" +- "and\t%5, %5, %3\;" +- "and\t%6, %0, %4\;" +- "or\t%6, %6, %5\;" +- "sc.w.rl\t%5, %6, %1\;" +- "bnez\t%5, 1b"; ++ "lr.w%I3\t%0, %1\;" ++ "\t%6, %0, %2\;" ++ "and\t%6, %6, %4\;" ++ "and\t%7, %0, %5\;" ++ "or\t%7, %7, %6\;" ++ "sc.w%J3\t%6, %7, %1\;" ++ "bnez\t%6, 1b"; + } + [(set (attr "length") (const_int 28))]) + +@@ -151,6 +152,7 @@ + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; + rtx value = operands[2]; ++ rtx model = operands[3]; + rtx aligned_mem = gen_reg_rtx (SImode); + rtx shift = gen_reg_rtx (SImode); + rtx mask = gen_reg_rtx (SImode); +@@ -162,7 +164,7 @@ + riscv_lshift_subword (mode, value, shift, &shifted_value); + + emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem, +- shifted_value, ++ shifted_value, model, + mask, not_mask)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, +@@ -180,22 +182,23 @@ + (unspec_volatile:SI + [(not:SI (and:SI (match_dup 1) + (match_operand:SI 2 "register_operand" "rI"))) ;; value for op +- (match_operand:SI 3 "register_operand" "rI")] ;; mask ++ (match_operand:SI 3 "const_int_operand")] ;; mask + UNSPEC_SYNC_OLD_OP_SUBWORD)) +- (match_operand:SI 4 "register_operand" "rI") ;; not_mask +- (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 +- (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 ++ (match_operand:SI 4 "register_operand" "rI") ;; mask ++ (match_operand:SI 5 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 ++ (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aqrl\t%0, %1\;" +- "and\t%5, %0, %2\;" +- "not\t%5, %5\;" +- "and\t%5, %5, %3\;" +- "and\t%6, %0, %4\;" +- "or\t%6, %6, %5\;" +- "sc.w.rl\t%5, %6, %1\;" +- "bnez\t%5, 1b"; ++ "lr.w%I3\t%0, %1\;" ++ "and\t%6, %0, %2\;" ++ "not\t%6, %6\;" ++ "and\t%6, %6, %4\;" ++ "and\t%7, %0, %5\;" ++ "or\t%7, %7, %6\;" ++ "sc.w%J3\t%6, %7, %1\;" ++ "bnez\t%6, 1b"; + } + [(set (attr "length") (const_int 32))]) + +@@ -216,6 +219,7 @@ + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; + rtx value = operands[2]; ++ rtx model = operands[3]; + rtx aligned_mem = gen_reg_rtx (SImode); + rtx shift = gen_reg_rtx (SImode); + rtx mask = gen_reg_rtx (SImode); +@@ -228,7 +232,8 @@ + + emit_insn (gen_subword_atomic_fetch_strong_ (old, aligned_mem, + shifted_value, +- mask, not_mask)); ++ model, mask, ++ not_mask)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, + gen_lowpart (QImode, shift))); +@@ -261,6 +266,7 @@ + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; + rtx value = operands[2]; ++ rtx model = operands[3]; + rtx aligned_mem = gen_reg_rtx (SImode); + rtx shift = gen_reg_rtx (SImode); + rtx mask = gen_reg_rtx (SImode); +@@ -272,7 +278,8 @@ + riscv_lshift_subword (mode, value, shift, &shifted_value); + + emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem, +- shifted_value, not_mask)); ++ shifted_value, model, ++ not_mask)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, + gen_lowpart (QImode, shift))); +@@ -286,18 +293,19 @@ + (match_operand:SI 1 "memory_operand" "+A")) ;; mem location + (set (match_dup 1) + (unspec_volatile:SI +- [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value +- (match_operand:SI 3 "reg_or_0_operand" "rI")] ;; not_mask ++ [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value ++ (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_EXCHANGE_SUBWORD)) +- (clobber (match_scratch:SI 4 "=&r"))] ;; tmp_1 ++ (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aqrl\t%0, %1\;" +- "and\t%4, %0, %3\;" +- "or\t%4, %4, %2\;" +- "sc.w.rl\t%4, %4, %1\;" +- "bnez\t%4, 1b"; ++ "lr.w%I3\t%0, %1\;" ++ "and\t%5, %0, %4\;" ++ "or\t%5, %5, %2\;" ++ "sc.w%J3\t%5, %5, %1\;" ++ "bnez\t%5, 1b"; + } + [(set (attr "length") (const_int 20))]) + +@@ -313,10 +321,15 @@ + (clobber (match_scratch:GPR 6 "=&r"))] + "TARGET_ATOMIC" + { ++ enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); ++ enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); ++ /* Find the union of the two memory models so we can satisfy both success ++ and failure memory models. */ ++ operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure)); + return "1:\;" +- "lr..aqrl\t%0,%1\;" ++ "lr.%I5\t%0,%1\;" + "bne\t%0,%z2,1f\;" +- "sc..rl\t%6,%z3,%1\;" ++ "sc.%J5\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } +@@ -440,9 +453,15 @@ + emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask)); + emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask)); + ++ enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); ++ enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); ++ /* Find the union of the two memory models so we can satisfy both success ++ and failure memory models. */ ++ rtx model = GEN_INT (riscv_union_memmodels (model_success, model_failure)); ++ + emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem, + shifted_o, shifted_n, +- mask, not_mask)); ++ model, mask, not_mask)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, + gen_lowpart (QImode, shift))); +@@ -459,19 +478,20 @@ + (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value + (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value + UNSPEC_COMPARE_AND_SWAP_SUBWORD)) +- (match_operand:SI 4 "register_operand" "rI") ;; mask +- (match_operand:SI 5 "register_operand" "rI") ;; not_mask +- (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 ++ (match_operand:SI 4 "const_int_operand") ;; model ++ (match_operand:SI 5 "register_operand" "rI") ;; mask ++ (match_operand:SI 6 "register_operand" "rI") ;; not_mask ++ (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aqrl\t%0, %1\;" +- "and\t%6, %0, %4\;" +- "bne\t%6, %z2, 1f\;" +- "and\t%6, %0, %5\;" +- "or\t%6, %6, %3\;" +- "sc.w.rl\t%6, %6, %1\;" +- "bnez\t%6, 1b\;" ++ "lr.w%I4\t%0, %1\;" ++ "and\t%7, %0, %5\;" ++ "bne\t%7, %z2, 1f\;" ++ "and\t%7, %0, %6\;" ++ "or\t%7, %7, %3\;" ++ "sc.w%J4\t%7, %7, %1\;" ++ "bnez\t%7, 1b\;" + "1:"; + } + [(set (attr "length") (const_int 28))]) +-- +2.39.3 + diff --git a/74abe200bc9b06e10f0f3cad74f11da4fae90cd3.patch b/74abe200bc9b06e10f0f3cad74f11da4fae90cd3.patch new file mode 100644 index 0000000..1296270 --- /dev/null +++ b/74abe200bc9b06e10f0f3cad74f11da4fae90cd3.patch @@ -0,0 +1,87 @@ +From 74abe200bc9b06e10f0f3cad74f11da4fae90cd3 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:56:33 -0700 +Subject: [PATCH] RISC-V: Strengthen atomic stores + +This change makes atomic stores strictly stronger than table A.6 of the +ISA manual. This mapping makes the overall patchset compatible with +table A.7 as well. + +2023-04-27 Patrick O'Neill + + PR target/89835 + +gcc/ChangeLog: + + * config/riscv/sync.md (atomic_store): Use simple store + instruction in combination with fence(s). + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/pr89835.c: New test. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 21 ++++++++++++++++++--- + gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ + 2 files changed, 27 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 5620d6ffa587..1acb78a9ae4c 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -56,7 +56,9 @@ + + ;; Atomic memory operations. + +-;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. ++;; Implement atomic stores with conservative fences. Fall back to fences for ++;; atomic loads. ++;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. + (define_insn "atomic_store" + [(set (match_operand:GPR 0 "memory_operand" "=A") + (unspec_volatile:GPR +@@ -64,9 +66,22 @@ + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "TARGET_ATOMIC" +- "%F2amoswap.%A2 zero,%z1,%0" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ model = memmodel_base (model); ++ ++ if (model == MEMMODEL_SEQ_CST) ++ return "fence\trw,w\;" ++ "s\t%z1,%0\;" ++ "fence\trw,rw"; ++ if (model == MEMMODEL_RELEASE) ++ return "fence\trw,w\;" ++ "s\t%z1,%0"; ++ else ++ return "s\t%z1,%0"; ++ } + [(set_attr "type" "atomic") +- (set (attr "length") (const_int 8))]) ++ (set (attr "length") (const_int 12))]) + + (define_insn "atomic_" + [(set (match_operand:GPR 0 "memory_operand" "+A") +diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c +new file mode 100644 +index 000000000000..ab190e11b608 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pr89835.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* Verify that relaxed atomic stores use simple store instuctions. */ ++/* { dg-final { scan-assembler-not "amoswap" } } */ ++ ++void ++foo(int bar, int baz) ++{ ++ __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); ++} +-- +2.39.3 + diff --git a/76ae6cd70f2ad4137a6d0ce32f618bc6ef2ca0b9.patch b/76ae6cd70f2ad4137a6d0ce32f618bc6ef2ca0b9.patch new file mode 100644 index 0000000..626eb8b --- /dev/null +++ b/76ae6cd70f2ad4137a6d0ce32f618bc6ef2ca0b9.patch @@ -0,0 +1,80 @@ +From 76ae6cd70f2ad4137a6d0ce32f618bc6ef2ca0b9 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:44:33 -0700 +Subject: [PATCH] RISC-V: Eliminate SYNC memory models + +Remove references to MEMMODEL_SYNC_* models by converting via +memmodel_base(). + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and + sanitize memmodel input with memmodel_base. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/riscv.cc | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 9c626904e893..11b897aca5c4 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -4294,14 +4294,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) + { + case MEMMODEL_ACQ_REL: + case MEMMODEL_SEQ_CST: +- case MEMMODEL_SYNC_SEQ_CST: + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: +- case MEMMODEL_SYNC_ACQUIRE: + return true; + + case MEMMODEL_RELEASE: +- case MEMMODEL_SYNC_RELEASE: + case MEMMODEL_RELAXED: + return false; + +@@ -4320,14 +4317,11 @@ riscv_memmodel_needs_release_fence (enum memmodel model) + { + case MEMMODEL_ACQ_REL: + case MEMMODEL_SEQ_CST: +- case MEMMODEL_SYNC_SEQ_CST: + case MEMMODEL_RELEASE: +- case MEMMODEL_SYNC_RELEASE: + return true; + + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: +- case MEMMODEL_SYNC_ACQUIRE: + case MEMMODEL_RELAXED: + return false; + +@@ -4366,6 +4360,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) + } + machine_mode mode = GET_MODE (op); + enum rtx_code code = GET_CODE (op); ++ const enum memmodel model = memmodel_base (INTVAL (op)); + + switch (letter) + { +@@ -4503,12 +4498,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) + break; + + case 'A': +- if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) ++ if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'F': +- if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) ++ if (riscv_memmodel_needs_release_fence (model)) + fputs ("fence iorw,ow; ", file); + break; + +-- +2.39.3 + diff --git a/93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch b/93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch new file mode 100644 index 0000000..a67370e --- /dev/null +++ b/93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch @@ -0,0 +1,37 @@ +From 93c4226585cc53fd86dfa3ca2d70d5b417d960b3 Mon Sep 17 00:00:00 2001 +From: xuli +Date: Tue, 22 Aug 2023 06:21:00 +0000 +Subject: [PATCH] RISCV: Fix PR111074 [GCC13 BUG] + +his patch fixes this issue happens on GCC-13. +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 + +This patch should be backported to GCC-13. +GCC-14 has rewritten propagate_avl function, so there is no issue. + +PR target/111074 + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix bug. +--- + gcc/config/riscv/riscv-vsetvl.cc | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index 789eb04b78d0..bd45cb97e63b 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -1183,6 +1183,9 @@ extract_single_source (set_info *set) + return nullptr; + hash_set sets = get_all_sets (set, true, false, true); + ++ if (sets.is_empty ()) ++ return nullptr; ++ + insn_info *first_insn = (*sets.begin ())->insn (); + if (first_insn->is_artificial ()) + return nullptr; +-- +2.39.3 + diff --git a/97672bd599e32ec6d488a7532b4ad15311810a46.patch b/97672bd599e32ec6d488a7532b4ad15311810a46.patch new file mode 100644 index 0000000..270e2fa --- /dev/null +++ b/97672bd599e32ec6d488a7532b4ad15311810a46.patch @@ -0,0 +1,473 @@ +From 97672bd599e32ec6d488a7532b4ad15311810a46 Mon Sep 17 00:00:00 2001 +From: Juzhe-Zhong +Date: Wed, 9 Aug 2023 18:51:42 +0800 +Subject: [PATCH] RISC-V: Fix VLMAX AVL incorrect local anticipate [VSETVL + PASS] + +Realize we have a bug in VSETVL PASS which is triggered by strided_load_run-1.c in RV32 system. + +FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test +FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test +FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test +FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test + +This is because VSETVL PASS incorrect hoist vsetvl instruction: + +... + 10156: 0d9075d7 vsetvli a1,zero,e64,m2,ta,ma ---> pollute 'a1' register which will be used by following insns. + 1015a: 01d586b3 add a3,a1,t4 --------> use 'a1' + 1015e: 5e070257 vmv.v.v v4,v14 + 10162: b7032257 vmacc.vv v4,v6,v16 + 10166: 26440257 vand.vv v4,v4,v8 + 1016a: 22880227 vs2r.v v4,(a6) + 1016e: 00b6b7b3 sltu a5,a3,a1 + 10172: 22888227 vs2r.v v4,(a7) + 10176: 9e60b157 vmv2r.v v2,v6 + 1017a: 97ba add a5,a5,a4 + 1017c: a6a62157 vmadd.vv v2,v12,v10 + 10180: 26240157 vand.vv v2,v2,v8 + 10184: 22830127 vs2r.v v2,(t1) + 10188: 873e mv a4,a5 + 1018a: 982a add a6,a6,a0 + 1018c: 98aa add a7,a7,a0 + 1018e: 932a add t1,t1,a0 + 10190: 85b6 mv a1,a3 -----> set 'a1' +... + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): + Fix incorrect anticipate info. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Adjust tests. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Ditto. +--- + gcc/config/riscv/riscv-vsetvl.cc | 4 ++- + .../riscv/rvv/vsetvl/vlmax_back_prop-1.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_back_prop-2.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_back_prop-24.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 31 +++++++++---------- + .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 30 +++++++++--------- + .../riscv/rvv/vsetvl/vlmax_back_prop-3.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_back_prop-36.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_back_prop-4.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_conflict-7.c | 2 +- + .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 10 +++--- + .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 14 ++++----- + .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c | 4 +-- + 13 files changed, 53 insertions(+), 54 deletions(-) + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index fbd269881064..789eb04b78d0 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -330,7 +330,9 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) + if (dem.has_avl_reg ()) + { + /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ +- if (!vlmax_avl_p (dem.get_avl ())) ++ rtx avl ++ = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); ++ if (!vlmax_avl_p (avl)) + { + set_info *set = dem.get_avl_source (); + /* If it's undefined, it's not anticipatable conservatively. */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c +index b0c40e8a0cb2..0bddcd78e9b4 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c +@@ -33,4 +33,4 @@ void f (void * restrict in, void * restrict out, int n, int cond) + + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c +index a09f50439249..b0a82df41a8e 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c +@@ -47,4 +47,4 @@ void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) + } + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c +index bc98e5f8269f..fe41d15cb281 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c +@@ -30,7 +30,7 @@ void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) + *(vint32mf2_t*)(out + 7000) = v; + + for (int i = 0; i < n; i++) { +- vbool64_t v; ++ vbool64_t v = *(vbool64_t*)(in + i + 9000); + *(vbool64_t*)(out + i + 700) = v; + } + } +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c +index 0a10827daf51..c566f8a4751d 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c +@@ -10,7 +10,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 100) = v; + for (int i = 0; i < n; i++) + { +- vint16mf4_t v2; ++ vint16mf4_t v2 = __riscv_vmv_v_x_i16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vint16mf4_t*)(out + i + 100) = v2; + } + } else if (cond == 1) { +@@ -18,7 +18,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 200) = v; + for (int i = 0; i < n; i++) + { +- vint32mf2_t v2; ++ vint32mf2_t v2 = __riscv_vmv_v_x_i32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vint32mf2_t*)(out + i + 200) = v2; + } + } else if (cond == 2) { +@@ -26,7 +26,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 300) = v; + for (int i = 0; i < n; i++) + { +- vint8mf8_t v2; ++ vint8mf8_t v2 = __riscv_vmv_v_x_i8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vint8mf8_t*)(out + i + 300) = v2; + } + } else if (cond == 3) { +@@ -34,7 +34,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 400) = v; + for (int i = 0; i < n; i++) + { +- vint64m1_t v2; ++ vint64m1_t v2 = __riscv_vmv_v_x_i64m1 (0, __riscv_vsetvlmax_e64m1 ()); + *(vint64m1_t*)(out + i + 400) = v2; + } + } else if (cond == 4) { +@@ -42,7 +42,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 500) = v; + for (int i = 0; i < n; i++) + { +- vfloat32mf2_t v2; ++ vfloat32mf2_t v2 = __riscv_vfmv_v_f_f32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vfloat32mf2_t*)(out + i + 500) = v2; + } + } else if (cond == 5) { +@@ -50,7 +50,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 600) = v; + for (int i = 0; i < n; i++) + { +- vuint16mf4_t v2; ++ vuint16mf4_t v2 = __riscv_vmv_v_x_u16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vuint16mf4_t*)(out + i + 600) = v2; + } + } else if (cond == 6) { +@@ -58,7 +58,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 700) = v; + for (int i = 0; i < n; i++) + { +- vuint32mf2_t v2; ++ vuint32mf2_t v2 = __riscv_vmv_v_x_u32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vuint32mf2_t*)(out + i + 700) = v2; + } + } else if (cond == 7) { +@@ -66,7 +66,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 800) = v; + for (int i = 0; i < n; i++) + { +- vuint8mf8_t v2; ++ vuint8mf8_t v2 = __riscv_vmv_v_x_u8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vuint8mf8_t*)(out + i + 800) = v2; + } + } else if (cond == 8) { +@@ -74,7 +74,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 900) = v; + for (int i = 0; i < n; i++) + { +- vuint64m1_t v2; ++ vuint64m1_t v2 = __riscv_vmv_v_x_u64m1 (0, __riscv_vsetvlmax_e64m1 ()); + *(vuint64m1_t*)(out + i + 900) = v2; + } + } else { +@@ -82,15 +82,14 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 1000) = v; + for (int i = 0; i < n; i++) + { +- vfloat32mf2_t v2; ++ vfloat32mf2_t v2 = *(vfloat32mf2_t*)(in + i + 9000); + *(vfloat32mf2_t*)(out + i + 1000) = v2; + } + } + } + +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 20 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c +index a65407513986..d0e752581889 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c +@@ -10,7 +10,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 100) = v; + for (int i = 0; i < n; i++) + { +- vint16mf4_t v2; ++ vint16mf4_t v2 = __riscv_vmv_v_x_i16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vint16mf4_t*)(out + i + 100) = v2; + } + } else if (cond == 1) { +@@ -18,7 +18,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 200) = v; + for (int i = 0; i < n; i++) + { +- vint32mf2_t v2; ++ vint32mf2_t v2 = __riscv_vmv_v_x_i32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vint32mf2_t*)(out + i + 200) = v2; + } + } else if (cond == 2) { +@@ -26,7 +26,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 300) = v; + for (int i = 0; i < n; i++) + { +- vint8mf8_t v2; ++ vint8mf8_t v2 = __riscv_vmv_v_x_i8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vint8mf8_t*)(out + i + 300) = v2; + } + } else if (cond == 3) { +@@ -34,7 +34,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 400) = v; + for (int i = 0; i < n; i++) + { +- vint64m1_t v2; ++ vint64m1_t v2 = __riscv_vmv_v_x_i64m1 (0, __riscv_vsetvlmax_e64m1 ()); + *(vint64m1_t*)(out + i + 400) = v2; + } + } else if (cond == 4) { +@@ -42,7 +42,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vint8mf8_t*)(out + 500) = v; + for (int i = 0; i < n; i++) + { +- vfloat32mf2_t v2; ++ vfloat32mf2_t v2 = __riscv_vfmv_v_f_f32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vfloat32mf2_t*)(out + i + 500) = v2; + } + } else if (cond == 5) { +@@ -50,7 +50,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 600) = v; + for (int i = 0; i < n; i++) + { +- vuint16mf4_t v2; ++ vuint16mf4_t v2 = __riscv_vmv_v_x_u16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vuint16mf4_t*)(out + i + 600) = v2; + } + } else if (cond == 6) { +@@ -58,7 +58,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 700) = v; + for (int i = 0; i < n; i++) + { +- vuint32mf2_t v2; ++ vuint32mf2_t v2 = __riscv_vmv_v_x_u32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vuint32mf2_t*)(out + i + 700) = v2; + } + } else if (cond == 7) { +@@ -66,7 +66,7 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 800) = v; + for (int i = 0; i < n; i++) + { +- vuint8mf8_t v2; ++ vuint8mf8_t v2 = __riscv_vmv_v_x_u8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vuint8mf8_t*)(out + i + 800) = v2; + } + } else if (cond == 8) { +@@ -74,16 +74,14 @@ void f (void * restrict in, void * restrict out, int n, int cond) + *(vuint8mf8_t*)(out + 900) = v; + for (int i = 0; i < n; i++) + { +- vuint64m1_t v2; ++ vuint64m1_t v2 = *(vuint64m1_t*)(in + i + 9000); + *(vuint64m1_t*)(out + i + 900) = v2; + } + } + } + +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 8 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 17 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c +index a16c5f506347..334c0756f993 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c +@@ -43,5 +43,5 @@ void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) + } + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c +index a6009b74101d..9be774c958b5 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c +@@ -37,7 +37,7 @@ void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, i + } + for (int i = 0; i < n; i++) + { +- vint8mf8_t v1; ++ vint8mf8_t v1 = *(vint8mf8_t*)(in2 + i + 20); + *(vint8mf8_t*)(out + i + 10) = v1; + } + } +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c +index fd2ba4470e6f..2f7f0ce81dac 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c +@@ -100,5 +100,5 @@ void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) + } + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c +index 60ad108666f8..b5ba532db098 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c +@@ -20,6 +20,6 @@ void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, si + } + } + +-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {j\s+\.L[0-9]+\s+\.L[0-9]+:\s+vlm\.v} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c +index f416a231f0e0..1fc97f8b6f2d 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c +@@ -6,7 +6,7 @@ + void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond) + { + for (int i = 0; i < n; i++) { +- vint16mf4_t v; ++ vint16mf4_t v = __riscv_vmv_v_x_i16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vint16mf4_t*)(out + i + 700) = v; + } + for (int i = 0; i < n; i++) { +@@ -19,15 +19,15 @@ void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n + a[i] = a[i] - b[i]; + } + for (int i = 0; i < n; i++) { +- vint32mf2_t v; ++ vint32mf2_t v = __riscv_vmv_v_x_i32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vint32mf2_t*)(out + i + 7000) = v; + } + for (int i = 0; i < n; i++) { +- vint64m1_t v; ++ vint64m1_t v = __riscv_vmv_v_x_i64m1 (0, __riscv_vsetvlmax_e64m1 ()); + *(vint64m1_t*)(out + i + 8000) = v; + } + for (int i = 0; i < n; i++) { +- vint8mf8_t v; ++ vint8mf8_t v = __riscv_vmv_v_x_i8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vint8mf8_t*)(out + i + 9000) = v; + } + } +@@ -36,4 +36,4 @@ void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c +index a39b48ccb998..f3b37661fbeb 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c +@@ -6,7 +6,7 @@ + void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond) + { + for (int i = 0; i < n; i++) { +- vint16mf4_t v; ++ vint16mf4_t v = __riscv_vmv_v_x_i16mf4 (0, __riscv_vsetvlmax_e16mf4 ()); + *(vint16mf4_t*)(out + i + 700) = v; + } + for (int i = 0; i < n; i++) { +@@ -19,27 +19,27 @@ void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n + a[i] = a[i] - b[i]; + } + for (int i = 0; i < n; i++) { +- vint32mf2_t v; ++ vint32mf2_t v = __riscv_vmv_v_x_i32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vint32mf2_t*)(out + i + 7000) = v; + } + for (int i = 0; i < n; i++) { +- vint16mf2_t v; ++ vint16mf2_t v = __riscv_vmv_v_x_i16mf2 (0, __riscv_vsetvlmax_e16mf2 ()); + *(vint16mf2_t*)(out + i + 777) = v; + } + for (int i = 0; i < n; i++) { +- vint64m1_t v; ++ vint64m1_t v = __riscv_vmv_v_x_i64m1 (0, __riscv_vsetvlmax_e64m1 ()); + *(vint64m1_t*)(out + i + 8000) = v; + } + for (int i = 0; i < n; i++) { +- vfloat32mf2_t v; ++ vfloat32mf2_t v = __riscv_vfmv_v_f_f32mf2 (0, __riscv_vsetvlmax_e32mf2 ()); + *(vfloat32mf2_t*)(out + i + 7777) = v; + } + for (int i = 0; i < n; i++) { +- vuint16mf2_t v; ++ vuint16mf2_t v = __riscv_vmv_v_x_u16mf2 (0, __riscv_vsetvlmax_e16mf2 ()); + *(vuint16mf2_t*)(out + i + 888) = v; + } + for (int i = 0; i < n; i++) { +- vint8mf8_t v; ++ vint8mf8_t v = __riscv_vmv_v_x_i8mf8 (0, __riscv_vsetvlmax_e8mf8 ()); + *(vint8mf8_t*)(out + i + 9000) = v; + } + } +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c +index 1ab92df0fdca..8e04fe8c9f6f 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c +@@ -55,6 +55,6 @@ void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n + /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ + /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ +-/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 11 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */ +-- +2.39.3 + diff --git a/a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch b/a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch new file mode 100644 index 0000000..f20414a --- /dev/null +++ b/a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch @@ -0,0 +1,30 @@ +From a8a7ba2e295908f40bb6f3b0965c298fb8228e22 Mon Sep 17 00:00:00 2001 +From: Juzhe-Zhong +Date: Wed, 23 Aug 2023 07:06:50 +0800 +Subject: [PATCH] RISC-V: Add riscv-vsetvl.def to t-riscv + +This patch will be backport to GCC 13 and commit to trunk. +gcc/ChangeLog: + + * config/riscv/t-riscv: Add riscv-vsetvl.def +--- + gcc/config/riscv/t-riscv | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv +index 1252d6f851ac..f3ce66ccdd4f 100644 +--- a/gcc/config/riscv/t-riscv ++++ b/gcc/config/riscv/t-riscv +@@ -62,7 +62,8 @@ riscv-vsetvl.o: $(srcdir)/config/riscv/riscv-vsetvl.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \ + $(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-config.h \ + insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h \ +- predict.h profile-count.h $(srcdir)/config/riscv/riscv-vsetvl.h ++ predict.h profile-count.h $(srcdir)/config/riscv/riscv-vsetvl.h \ ++ $(srcdir)/config/riscv/riscv-vsetvl.def + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/riscv-vsetvl.cc + +-- +2.39.3 + diff --git a/cb398a612ed5f5110adaaaea338447b6e933067d.patch b/cb398a612ed5f5110adaaaea338447b6e933067d.patch new file mode 100644 index 0000000..ee3bbd8 --- /dev/null +++ b/cb398a612ed5f5110adaaaea338447b6e933067d.patch @@ -0,0 +1,117 @@ +From cb398a612ed5f5110adaaaea338447b6e933067d Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 5 Apr 2023 09:48:06 -0700 +Subject: [PATCH] RISC-V: Eliminate AMO op fences + +Atomic operations with the appropriate bits set already enfore release +semantics. Remove unnecessary release fences from atomic ops. + +This change brings AMO ops in line with table A.6 of the ISA manual. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/riscv.cc + (riscv_memmodel_needs_amo_release): Change function name. + (riscv_print_operand): Remove unneeded %F case. + * config/riscv/sync.md: Remove unneeded fences. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/riscv.cc | 16 +++++----------- + gcc/config/riscv/sync.md | 12 ++++++------ + 2 files changed, 11 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index df55c427b1b3..951f6b5cf42d 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -4307,11 +4307,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) + } + } + +-/* Return true if a FENCE should be emitted to before a memory access to +- implement the release portion of memory model MODEL. */ ++/* Return true if the .RL suffix should be added to an AMO to implement the ++ release portion of memory model MODEL. */ + + static bool +-riscv_memmodel_needs_release_fence (enum memmodel model) ++riscv_memmodel_needs_amo_release (enum memmodel model) + { + switch (model) + { +@@ -4337,7 +4337,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) + 'R' Print the low-part relocation associated with OP. + 'C' Print the integer branch condition for comparison OP. + 'A' Print the atomic operation suffix for memory model OP. +- 'F' Print a FENCE if the memory model requires a release. + 'z' Print x0 if OP is zero, otherwise print OP normally. + 'i' Print i if the operand is not a register. + 'S' Print shift-index of single-bit mask OP. +@@ -4499,19 +4498,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) + + case 'A': + if (riscv_memmodel_needs_amo_acquire (model) +- && riscv_memmodel_needs_release_fence (model)) ++ && riscv_memmodel_needs_amo_release (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); +- else if (riscv_memmodel_needs_release_fence (model)) ++ else if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + +- case 'F': +- if (riscv_memmodel_needs_release_fence (model)) +- fputs ("fence iorw,ow; ", file); +- break; +- + case 'i': + if (code != REG) + fputs ("i", file); +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 1acb78a9ae4c..9a3b57bd09fd 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -91,9 +91,9 @@ + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] + "TARGET_ATOMIC" +- "%F2amo.%A2 zero,%z1,%0" ++ "amo.%A2\tzero,%z1,%0" + [(set_attr "type" "atomic") +- (set (attr "length") (const_int 8))]) ++ (set (attr "length") (const_int 4))]) + + (define_insn "atomic_fetch_" + [(set (match_operand:GPR 0 "register_operand" "=&r") +@@ -105,9 +105,9 @@ + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] + "TARGET_ATOMIC" +- "%F3amo.%A3 %0,%z2,%1" ++ "amo.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") +- (set (attr "length") (const_int 8))]) ++ (set (attr "length") (const_int 4))]) + + (define_insn "subword_atomic_fetch_strong_" + [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem +@@ -247,9 +247,9 @@ + (set (match_dup 1) + (match_operand:GPR 2 "register_operand" "0"))] + "TARGET_ATOMIC" +- "%F3amoswap.%A3 %0,%z2,%1" ++ "amoswap.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") +- (set (attr "length") (const_int 8))]) ++ (set (attr "length") (const_int 4))]) + + (define_expand "atomic_exchange" + [(match_operand:SHORT 0 "register_operand") ;; old value at mem +-- +2.39.3 + diff --git a/e0bd6c2bee0614fc4112a0a86a808edd0d550b6f.patch b/e0bd6c2bee0614fc4112a0a86a808edd0d550b6f.patch new file mode 100644 index 0000000..e2e5800 --- /dev/null +++ b/e0bd6c2bee0614fc4112a0a86a808edd0d550b6f.patch @@ -0,0 +1,63 @@ +From e0bd6c2bee0614fc4112a0a86a808edd0d550b6f Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Fri, 21 Apr 2023 13:11:35 -0700 +Subject: [PATCH] RISC-V: Enforce subword atomic LR/SC SEQ_CST + +Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs +recommended by table A.6 of the ISA manual. + +2023-04-27 Patrick O'Neill + +gcc/ChangeLog: + + * config/riscv/sync.md: Change LR.aq/SC.rl pairs into + sequentially consistent LR.aqrl/SC.rl pairs. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 192745282626..0c83ef046070 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -109,7 +109,7 @@ + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aq\t%0, %1\;" ++ "lr.w.aqrl\t%0, %1\;" + "\t%5, %0, %2\;" + "and\t%5, %5, %3\;" + "and\t%6, %0, %4\;" +@@ -173,7 +173,7 @@ + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aq\t%0, %1\;" ++ "lr.w.aqrl\t%0, %1\;" + "and\t%5, %0, %2\;" + "not\t%5, %5\;" + "and\t%5, %5, %3\;" +@@ -278,7 +278,7 @@ + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aq\t%0, %1\;" ++ "lr.w.aqrl\t%0, %1\;" + "and\t%4, %0, %3\;" + "or\t%4, %4, %2\;" + "sc.w.rl\t%4, %4, %1\;" +@@ -443,7 +443,7 @@ + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" +- "lr.w.aq\t%0, %1\;" ++ "lr.w.aqrl\t%0, %1\;" + "and\t%6, %0, %4\;" + "bne\t%6, %z2, 1f\;" + "and\t%6, %0, %5\;" +-- +2.39.3 + diff --git a/ffd676ef2c9849231626a532343c7ec908558c33.patch b/ffd676ef2c9849231626a532343c7ec908558c33.patch new file mode 100644 index 0000000..86ce1d8 --- /dev/null +++ b/ffd676ef2c9849231626a532343c7ec908558c33.patch @@ -0,0 +1,239 @@ +From ffd676ef2c9849231626a532343c7ec908558c33 Mon Sep 17 00:00:00 2001 +From: yulong +Date: Tue, 8 Aug 2023 12:12:32 +0800 +Subject: [PATCH] RISC-V: Fix a bug that causes an error insn. +MIME-Version: 1.0 +Content-Type: text/plain; charset=utf8 +Content-Transfer-Encoding: 8bit + +I test the following rvv intrinsics. +vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { + return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); +} +And I got an error info,t hat is error: + unrecognizable insn:(insn 17 16 18 2 + (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI + (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 日 [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE + (vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 日 zero)] UNSPEC_VUNDEF) + (reg/v:RVVMF64BI 137 [ mask ])) + (unspec:RVVM1DI[(reg:sI 日 zero)] UNSPEC_VUNDEF))) + +This patch fix it. + +gcc/ChangeLog: + + * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/vslide1down-1.c: New test. + * gcc.target/riscv/rvv/base/vslide1down-2.c: New test. + * gcc.target/riscv/rvv/base/vslide1down-3.c: New test. + * gcc.target/riscv/rvv/base/vslide1up-1.c: New test. + * gcc.target/riscv/rvv/base/vslide1up-2.c: New test. + * gcc.target/riscv/rvv/base/vslide1up-3.c: New test. +--- + gcc/config/riscv/riscv-v.cc | 5 ++--- + .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/vslide1up-1.c | 22 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/vslide1up-2.c | 22 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/vslide1up-3.c | 22 +++++++++++++++++++ + 7 files changed, 134 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c + +diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc +index 392f5d02e17c..722ed27bd267 100644 +--- a/gcc/config/riscv/riscv-v.cc ++++ b/gcc/config/riscv/riscv-v.cc +@@ -701,9 +701,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode, + CONSTM1_RTX (demote_mask_mode), merge, temp, + demote_scalar_op2, vl_x2, ta, ma, ops[8])); + +- if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))) +- return true; +- else ++ if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))) ++ && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2])))) + emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1], + force_vector_length_operand (ops[5]), ops[6], + ops[8])); +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c +new file mode 100644 +index 000000000000..541745be2a1e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c +new file mode 100644 +index 000000000000..9b5a240a9e69 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c +new file mode 100644 +index 000000000000..7b05c85a243a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c +new file mode 100644 +index 000000000000..74e8e5e63f70 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c +new file mode 100644 +index 000000000000..e7e2ee950c73 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c +new file mode 100644 +index 000000000000..b0b3af24e644 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ ++ ++#include "riscv_vector.h" ++ ++vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl); ++} ++ ++vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl); ++} ++ ++vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl); ++} ++ ++vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) { ++ return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl); ++} ++ ++/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */ +-- +2.39.3 + diff --git a/gcc.spec b/gcc.spec index 45edab1..5904df7 100644 --- a/gcc.spec +++ b/gcc.spec @@ -93,7 +93,7 @@ %else %global build_libatomic 0 %endif -%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 +%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 riscv64 %global build_libitm 1 %else %global build_libitm 0 @@ -136,7 +136,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: gcc Version: %{gcc_version} -Release: %{gcc_release}%{?dist} +Release: %{gcc_release}.1.riscv64%{?dist} # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -291,6 +291,24 @@ Patch50: isl-rh2155127.patch Patch100: gcc13-fortran-fdec-duplicates.patch +# riscv64 (approved, merged in refs/heads/releases/gcc-13) +Patch20: 76ae6cd70f2ad4137a6d0ce32f618bc6ef2ca0b9.patch +Patch21: 4b6751b6a1fd054b33a57cfb942fb895b624f3e8.patch +Patch22: e0bd6c2bee0614fc4112a0a86a808edd0d550b6f.patch +Patch23: 0180b20de73778fe1e67060f66c7f47630aeb949.patch +Patch24: 687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6.patch +Patch25: 74abe200bc9b06e10f0f3cad74f11da4fae90cd3.patch +Patch26: cb398a612ed5f5110adaaaea338447b6e933067d.patch +Patch27: 71506544eef580f59e5816f0a48a67aebbe5eed5.patch +Patch28: 36a84e538bb9d3feb1762200074f39a1e9ff4fce.patch +Patch29: 0e42ac31fdeffdcec22f1935534693d4cef62e0b.patch +Patch30: 444d909b323d94639e60aab6c4089ff839c0f0e9.patch +Patch31: 1e9180b3298def6c01d9055d558fdb52231f8d2d.patch +Patch32: ffd676ef2c9849231626a532343c7ec908558c33.patch +Patch33: 97672bd599e32ec6d488a7532b4ad15311810a46.patch +Patch34: 93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch +Patch35: a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch + # On ARM EABI systems, we do want -gnueabi to be part of the # target triple. %ifnarch %{arm} @@ -982,6 +1000,13 @@ ISL_FLAG_PIC=-fPIC ISL_FLAG_PIC=-fpic %endif cd isl-build + +%ifarch riscv64 +# Update config.{sub,guess} scripts for riscv64 (the original ones are too old) +cp -f -v /usr/lib/rpm/%{_vendor}/config.guess ../../isl-%{isl_version}/config.guess +cp -f -v /usr/lib/rpm/%{_vendor}/config.sub ../../isl-%{isl_version}/config.sub +%endif + sed -i 's|libisl\([^-]\)|libgcc13privateisl\1|g' \ ../../isl-%{isl_version}/Makefile.{am,in} ../../isl-%{isl_version}/configure \ @@ -2537,6 +2562,9 @@ end %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/htmxlintrin.h %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/vecintrin.h %endif +%ifarch riscv64 +%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/riscv_vector.h +%endif %if %{build_libasan} %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/sanitizer %endif @@ -3453,6 +3481,13 @@ end %endif %changelog +* Fri Aug 25 2023 David Abdurachmanov 13.2.1-1.1.riscv64 +- Backport riscv64 specific patches (16 in total) from + refs/heads/releases/gcc-13 + +* Thu Aug 10 2023 David Abdurachmanov 13.2.1-1.0.riscv64 +- Adjust for riscv64 + * Fri Jul 28 2023 Jakub Jelinek 13.2.1-1 - update from releases/gcc-13 branch - GCC 13.2 release diff --git a/gcc13-libtool-no-rpath.patch b/gcc13-libtool-no-rpath.patch index 466c661..8429a4c 100644 --- a/gcc13-libtool-no-rpath.patch +++ b/gcc13-libtool-no-rpath.patch @@ -5,7 +5,7 @@ libtool sucks. rpath="$finalize_rpath" test "$mode" != relink && rpath="$compile_rpath$rpath" for libdir in $rpath; do -+ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64) continue;; esac ++ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64|/usr/lib/../lib64/lp64d) continue;; esac if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then if test -z "$hardcode_libdirs"; then @@ -13,7 +13,7 @@ libtool sucks. rpath= hardcode_libdirs= for libdir in $compile_rpath $finalize_rpath; do -+ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64) continue;; esac ++ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64|/usr/lib/../lib64/lp64d) continue;; esac if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then if test -z "$hardcode_libdirs"; then @@ -21,7 +21,7 @@ libtool sucks. rpath= hardcode_libdirs= for libdir in $finalize_rpath; do -+ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64) continue;; esac ++ case "$libdir" in /usr/lib|/usr/lib64|/usr/lib/../lib|/usr/lib/../lib64|/usr/lib/../lib64/lp64d) continue;; esac if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then if test -z "$hardcode_libdirs"; then