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4.4.0-4

This commit is contained in:
Jakub Jelinek 2009-05-06 18:06:19 +00:00
parent b03a15ac61
commit 6636b57642
11 changed files with 660 additions and 367 deletions
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2
.cvsignore
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@ -1,2 +1,2 @@
fastjar-0.97.tar.gz
gcc-4.4.0-20090427.tar.bz2
gcc-4.4.0-20090506.tar.bz2

82
gcc.spec
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@ -1,9 +1,9 @@
%define DATE 20090427
%define SVNREV 146836
%define DATE 20090506
%define SVNREV 147193
%define gcc_version 4.4.0
# Note, gcc_release must be integer, if you want to add suffixes to
# %{release}, append them after %{gcc_release} on Release: line.
%define gcc_release 3
%define gcc_release 4
%define _unpackaged_files_terminate_build 0
%define multilib_64_archs sparc64 ppc64 s390x x86_64
%define include_gappletviewer 1
@ -18,6 +18,7 @@
%else
%define build_cloog 1
%endif
%define build_libstdcxx_docs 1
# If you don't have already a usable gcc-java and libgcj for your arch,
# do on some arch which has it rpmbuild -bc --with java_tar gcc41.spec
# which creates libjava-classes-%{version}-%{release}.tar.bz2
@ -99,6 +100,10 @@ BuildRequires: libunwind >= 0.98
%if %{build_cloog}
BuildRequires: ppl >= 0.10, ppl-devel >= 0.10, cloog-ppl >= 0.15, cloog-ppl-devel >= 0.15
%endif
%if %{build_libstdcxx_docs}
BuildRequires: doxygen
BuildRequires: graphviz
%endif
Requires: cpp = %{version}-%{release}
# Need .eh_frame ld optimizations
# Need proper visibility support
@ -152,7 +157,10 @@ Patch26: gcc44-power7-2.patch
Patch27: gcc44-power7-3.patch
Patch28: gcc44-pr38757.patch
Patch29: gcc44-pr39856.patch
Patch30: gcc44-pr39903.patch
Patch30: gcc44-libstdc++-docs.patch
Patch31: gcc44-pr39666.patch
Patch32: gcc44-pr40035.patch
Patch33: gcc44-pr39942.patch
Patch1000: fastjar-0.97-segfault.patch
@ -217,6 +225,15 @@ This is the GNU implementation of the standard C++ libraries. This
package includes the header files and libraries needed for C++
development. This includes rewritten implementation of STL.
%package -n libstdc++-docs
Summary: Documentation for the GNU standard C++ library
Group: Development/Libraries
Autoreq: true
%description -n libstdc++-docs
Manual, doxygen generated API information and Frequently Asked Questions
for the GNU standard C++ library.
%package objc
Summary: Objective-C support for GCC
Group: Development/Languages
@ -443,7 +460,12 @@ which are required to compile with the GNAT.
%patch27 -p0 -b .power7-3~
%patch28 -p0 -b .pr38757~
%patch29 -p0 -b .pr39856~
%patch30 -p0 -b .pr39903~
%if %{build_libstdcxx_docs}
%patch30 -p0 -b .libstdc++-docs~
%endif
%patch31 -p0 -b .pr39666~
%patch32 -p0 -b .pr40035~
%patch33 -p0 -b .pr39942~
# This testcase doesn't compile.
rm libjava/testsuite/libjava.lang/PR35020*
@ -660,6 +682,14 @@ done
make -C gcc generated-manpages
for i in ../gcc/doc/*.texi; do mv -f $i.orig $i; done
# Make generated doxygen pages.
%if %{build_libstdcxx_docs}
cd %{gcc_target_platform}/libstdc++-v3
make doc-html-doxygen
make doc-man-doxygen
cd ../..
%endif
# Copy various doc files here and there
cd ..
mkdir -p rpm.doc/gfortran rpm.doc/objc
@ -710,10 +740,6 @@ tar cf - -T libjava-classes.list | bzip2 -9 > $RPM_SOURCE_DIR/libjava-classes-%{
%install
rm -fr $RPM_BUILD_ROOT
perl -pi -e \
's~href="l(ibstdc|atest)~href="http://gcc.gnu.org/onlinedocs/libstdc++/l\1~' \
libstdc++-v3/doc/html/api.html
cd obj-%{gcc_target_platform}
%if %{build_java}
@ -794,6 +820,16 @@ done
# shipping this for everybody is unnecessary.
rm -rf $RPM_BUILD_ROOT%{_prefix}/include/c++/%{gcc_version}/%{gcc_target_platform}/bits/stdc++.h.gch
%if %{build_libstdcxx_docs}
libstdcxx_doc_builddir=%{gcc_target_platform}/libstdc++-v3/doc/doxygen
mkdir -p ../rpm.doc/libstdc++-v3
cp -r -p ../libstdc++-v3/doc/html ../rpm.doc/libstdc++-v3/html
mv $libstdcxx_doc_builddir/html ../rpm.doc/libstdc++-v3/html/api
mkdir -p $RPM_BUILD_ROOT%{_mandir}
mv $libstdcxx_doc_builddir/man/man3 $RPM_BUILD_ROOT%{_mandir}/man3/
find ../rpm.doc/libstdc++-v3 -name \*~ | xargs rm
%endif
%ifarch sparcv9 sparc64
ln -f $RPM_BUILD_ROOT%{_prefix}/bin/%{gcc_target_platform}-gcc \
$RPM_BUILD_ROOT%{_prefix}/bin/sparc-%{_vendor}-%{_target_os}-gcc
@ -1441,7 +1477,14 @@ fi
%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_version}/libstdc++.so
%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_version}/libsupc++.a
%endif
%doc rpm.doc/changelogs/libstdc++-v3/ChangeLog* libstdc++-v3/README* libstdc++-v3/doc/html/
%doc rpm.doc/changelogs/libstdc++-v3/ChangeLog* libstdc++-v3/README*
%if %{build_libstdcxx_docs}
%files -n libstdc++-docs
%defattr(-,root,root)
%{_mandir}/man3/*
%doc rpm.doc/libstdc++-v3/html
%endif
%files objc
%defattr(-,root,root)
@ -1754,6 +1797,25 @@ fi
%doc rpm.doc/changelogs/libmudflap/ChangeLog*
%changelog
* Wed May 6 2009 Jakub Jelinek <jakub@redhat.com> 4.4.0-4
- update from gcc-4_4-branch
- PRs c++/40013, libgcj/39899, libstdc++/39868, libstdc++/39880,
libstdc++/39881, libstdc++/39882, libstdc++/39909, middle-end/39937,
rtl-optimization/39914, target/39565, testsuite/39769,
testsuite/39776, testsuite/39790, testsuite/39807,
tree-optimization/39941
- fix phiprop tuplification (#496400, PR tree-optimization/40022)
- don't add artificial default case label if switch labels already
cover the whole range (PR middle-end/39666)
- fix DSE with block reads (PR middle-end/40035)
- fix debuginfo for C++ typedef struct {...} T (PR debug/35463)
- remove some unnecessary padding on x86_64/i386 added for >= 4 control
flow insns in a 16-byte block (PR target/39942)
- don't create invalid DWARF location lists containing DW_OP_reg*
followed by DW_OP_deref*, instead use DW_OP_breg* 0 (#481675)
- add libstdc++-docs subpackage, move html manual to it, add doxygen
generated html and man pages
* Mon Apr 27 2009 Jakub Jelinek <jakub@redhat.com> 4.4.0-3
- update from gcc-4_4-branch
- PR bootstrap/39739

47
gcc44-libstdc++-docs.patch Normal file
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@ -0,0 +1,47 @@
--- libstdc++-v3/doc/html/index.html 2009-01-14 12:06:37.000000000 +0100
+++ libstdc++-v3/doc/html/index.html 2009-05-06 09:17:30.000000000 +0200
@@ -12,7 +12,8 @@
<div>
<h1>The GNU C++ Library Documentation</h1>
-<p>Copyright 2008 FSF</p>
+<p>Release 4.4.0</p>
+<p>Copyright 2008, 2009 FSF</p>
<p>
Permission is granted to copy, distribute and/or modify this
--- libstdc++-v3/doc/html/api.html 2009-04-20 21:21:15.000000000 +0200
+++ libstdc++-v3/doc/html/api.html 2009-05-06 09:17:24.000000000 +0200
@@ -17,27 +17,12 @@ useful for examining the signatures of p
the library classes, finding out what is in a particular include
file, looking at inheritance diagrams, etc.
</p><p>
-The source-level documentation for the most recent releases can be
-viewed online:
-</p><div class="itemizedlist"><ul type="disc"><li><p>
- <a class="ulink" href="libstdc++-html-USERS-3.4/index.html" target="_top">for the 3.4 release
+The source-level documentation can be viewed here:
+</p>
+<div class="itemizedlist"><ul type="disc">
+ <li><p>
+ <a class="ulink" href="api/index.html" target="_top">for the 4.4 release
</a>
- </p></li><li><p>
- <a class="ulink" href="libstdc++-html-USERS-4.1/index.html" target="_top">for the 4.1 release
- </a>
- </p></li><li><p>
- <a class="ulink" href="libstdc++-html-USERS-4.2/index.html" target="_top">for the 4.2 release
- </a>
- </p></li><li><p>
- <a class="ulink" href="libstdc++-html-USERS-4.3/index.html" target="_top">for the 4.3 release
- </a>
- </p></li><li><p>
- <a class="ulink" href="libstdc++-html-USERS-4.4/index.html" target="_top">for the 4.4 release
- </a>
- </p></li><li><p>
- <a class="ulink" href="latest-doxygen/index.html" target="_top">"the latest collection"
- </a>
- (For the main development tree; see the date on the first page.)
</p></li></ul></div><p>
This generated HTML collection, as above, is also available for download in the libstdc++ snapshots directory at
<code class="literal">&lt;URL:ftp://gcc.gnu.org/pub/gcc/libstdc++/doxygen/&gt;</code>.

61
gcc44-power7-2.patch
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@ -9,67 +9,6 @@
(vec_reload_and_reg_<mptrsize>): Allow for and of register
indirect to not generate insn not found message.
PR testsuite/39769
* gcc.dg/vmx/3a-04.c (test): Don't rely on floating point equality
for testing the results of estimate instructions.
* gcc.dg/vmx/3a-04m.c (test): Ditto.
* gcc.dg/vmx/3a-05.c (test): Ditto.
--- gcc/testsuite/gcc.dg/vmx/3a-05.c (revision 146069)
+++ gcc/testsuite/gcc.dg/vmx/3a-05.c (revision 146118)
@@ -14,9 +14,13 @@ f(vector float a, vector float b, vector
static void test()
{
- check(vec_all_eq(f(((vector float){2,3,5,7}),
+ check(vec_all_gt(f(((vector float){2,3,5,7}),
((vector float){11,13,17,19}),
((vector float){23,29,31,37})),
- ((vector float){16.9092026, 18.7693329, -2.8233242, -92.9472198})),
- "f");
+ ((vector float){16.90, 18.76, -2.83, -92.95}))
+ && vec_all_lt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+ ((vector float){16.91, 18.77, -2.82, -92.94})),
+ "f");
}
--- gcc/testsuite/gcc.dg/vmx/3a-04m.c (revision 146069)
+++ gcc/testsuite/gcc.dg/vmx/3a-04m.c (revision 146118)
@@ -10,9 +10,13 @@ f(vector float a, vector float b, vector
static void test()
{
- check(vec_all_eq(f(((vector float){2,3,5,7}),
+ check(vec_all_gt(f(((vector float){2,3,5,7}),
((vector float){11,13,17,19}),
((vector float){23,29,31,37})),
- ((vector float){23.1818085, 29.2307587, 32.2940826, 128.368393})),
+ ((vector float){23.18, 29.23, 32.29, 128.36}))
+ && vec_all_lt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+ ((vector float){23.19, 29.24, 32.30, 128.37})),
"f");
}
--- gcc/testsuite/gcc.dg/vmx/3a-04.c (revision 146069)
+++ gcc/testsuite/gcc.dg/vmx/3a-04.c (revision 146118)
@@ -10,9 +10,13 @@ f(vector float a, vector float b, vector
static void test()
{
- check(vec_all_eq(f(((vector float){2,3,5,7}),
+ check(vec_all_gt(f(((vector float){2,3,5,7}),
((vector float){11,13,17,19}),
((vector float){23,29,31,37})),
- ((vector float){23.1818085, 29.2307587, 32.2940826, 128.368393})),
+ ((vector float){23.18, 29.23, 32.29, 128.36}))
+ && vec_all_lt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+ ((vector float){23.19, 29.24, 32.30, 128.37})),
"f");
}
--- gcc/config/rs6000/vector.md (revision 146069)
+++ gcc/config/rs6000/vector.md (revision 146118)
@@ -129,14 +129,15 @@ (define_expand "reload_<VEC_R:mode>_<P:m

404
gcc44-power7-3.patch
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@ -1,3 +1,205 @@
2009-04-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (vector_vsel<mode>): Generate the insns
directly instead of calling VSX/Altivec expanders.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Map VSX
builtins that are identical to Altivec, to the Altivec vesion.
(altivec_overloaded_builtins): Add V2DF/V2DI sel, perm support.
(altivec_resolve_overloaded_builtin): Add V2DF/V2DI support.
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Rename VSX
splat functions.
(expand_vector_set): Merge V2DF/V2DI code.
(expand_vector_extract): Ditto.
(bdesc_3arg): Add more VSX builtins.
(bdesc_2arg): Ditto.
(bdesc_1arg): Ditto.
(rs6000_expand_ternop_builtin): Require xxpermdi 3rd argument to
be 2 bit-constant, and V2DF/V2DI set to be a 1 bit-constant.
(altivec_expand_builtin): Add support for VSX overloaded builtins.
(altivec_init_builtins): Ditto.
(rs6000_common_init_builtins): Ditto.
(rs6000_init_builtins): Add V2DI types and vector long support.
(rs6000_handle_altivec_attribute): Ditto.
(rs6000_mange_type): Ditto.
* config/rs6000/vsx.md (UNSPEC_*): Add new UNSPEC constants.
(vsx_vsel<mode>): Add support for all vector types, including
Altivec types.
(vsx_ftrunc<mode>2): Emit the correct instruction.
(vsx_x<VSv>r<VSs>i): New builtin rounding mode insns.
(vsx_x<VSv>r<VSs>ic): Ditto.
(vsx_concat_<mode>): Key off of VSX memory instructions being
generated instead of the vector arithmetic unit to enable V2DI
mode.
(vsx_extract_<mode>): Ditto.
(vsx_set_<mode>): Rewrite as an unspec.
(vsx_xxpermdi2_<mode>): Rename old vsx_xxpermdi_<mode> here. Key
off of VSX memory instructions instead of arithmetic unit.
(vsx_xxpermdi_<mode>): New insn for __builtin_vsx_xxpermdi.
(vsx_splat_<mode>): Rename from vsx_splat<mode>.
(vsx_xxspltw_<mode>): Change from V4SF only to V4SF/V4SI modes.
Fix up constraints. Key off of memory instructions instead of
arithmetic instructions to allow use with V4SI.
(vsx_xxmrghw_<mode>): Ditto.
(vsx_xxmrglw_<mode>): Ditto.
(vsx_xxsldwi_<mode>): Implement vector shift double by word
immediate.
* config/rs6000/rs6000.h (VSX_BUILTIN_*): Update for current
builtins being generated.
(RS6000_BTI_unsigned_V2DI): Add vector long support.
(RS6000_BTI_bool_long): Ditto.
(RS6000_BTI_bool_V2DI): Ditto.
(unsigned_V2DI_type_node): Ditto.
(bool_long_type_node): Ditto.
(bool_V2DI_type_node): Ditto.
* config/rs6000/altivec.md (altivec_vsel<mode>): Add '*' since we
don't need the generator function now. Use VSX instruction if
-mvsx.
(altivec_vmrghw): Use VSX instruction if -mvsx.
(altivec_vmrghsf): Ditto.
(altivec_vmrglw): Ditto.
(altivec_vmrglsf): Ditto.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document that under VSX, vector double/long are available.
testsuite/
* gcc.target/powerpc/vsx-builtin-3.c: New test for VSX builtins.
2009-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_E): New iterator to add V2DImode.
(vec_init<mode>): Use VEC_E instead of VEC_C iterator, to add
V2DImode support.
(vec_set<mode>): Ditto.
(vec_extract<mode>): Ditto.
* config/rs6000/predicates.md (easy_vector_constant): Add support
for setting TImode to 0.
* config/rs6000/rs6000.opt (-mvsx-vector-memory): Delete old debug
switch that is no longer used.
(-mvsx-vector-float): Ditto.
(-mvsx-vector-double): Ditto.
(-mvsx-v4sf-altivec-regs): Ditto.
(-mreload-functions): Ditto.
(-mallow-timode): New debug switch.
* config/rs6000/rs6000.c (rs6000_ira_cover_classes): New target
hook for IRA cover classes, to know that under VSX the float and
altivec registers are part of the same register class, but before
they weren't.
(TARGET_IRA_COVER_CLASSES): Set ira cover classes target hookd.
(rs6000_hard_regno_nregs): Key off of whether VSX/Altivec memory
instructions are supported, and not whether the vector unit has
arithmetic support to enable V2DI/TI mode.
(rs6000_hard_regno_mode_ok): Ditto.
(rs6000_init_hard_regno_mode_ok): Add V2DImode, TImode support.
Drop several of the debug switches.
(rs6000_emit_move): Force TImode constants to memory if we have
either Altivec or VSX.
(rs6000_builtin_conversion): Use correct insns for V2DI<->V2DF
conversions.
(rs6000_expand_vector_init): Add V2DI support.
(rs6000_expand_vector_set): Ditto.
(avoiding_indexed_address_p): Simplify tests to say if the mode
uses VSX/Altivec memory instructions we can't eliminate reg+reg
addressing.
(rs6000_legitimize_address): Move VSX/Altivec REG+REG support
before the large integer support.
(rs6000_legitimate_address): Add support for TImode in VSX/Altivec
registers.
(rs6000_emit_move): Ditto.
(def_builtin): Change internal error message to provide more
information.
(bdesc_2arg): Add conversion builtins.
(builtin_hash_function): New function for hashing all of the types
for builtin functions.
(builtin_hash_eq): Ditto.
(builtin_function_type): Ditto.
(builtin_mode_to_type): New static for builtin argument hashing.
(builtin_hash_table): Ditto.
(rs6000_common_init_builtins): Rewrite so that types for builtin
functions are only created when we need them, and use a hash table
to store all of the different argument combinations that are
created. Add support for VSX conversion builtins.
(rs6000_preferred_reload_class): Add TImode support.
(reg_classes_cannot_change_mode_class): Be stricter about VSX and
Altivec vector types.
(rs6000_emit_vector_cond_expr): Use VSX_MOVE_MODE, not
VSX_VECTOR_MOVE_MODE.
(rs6000_handle_altivec_attribute): Allow __vector long on VSX.
* config/rs6000/vsx.md (VSX_D): New iterator for vectors with
64-bit elements.
(VSX_M): New iterator for 128 bit types for moves, except for
TImode.
(VSm, VSs, VSr): Add TImode.
(VSr4, VSr5): New mode attributes for float<->double conversion.
(VSX_SPDP): New iterator for float<->double conversion.
(VS_spdp_*): New mode attributes for float<->double conversion.
(UNSPEC_VSX_*): Rename unspec constants to remove XV from the
names. Change all users.
(vsx_mov<mode>): Drop TImode support here.
(vsx_movti): New TImode support, allow GPRs, but favor VSX
registers.
(vsx_<VS_spdp_insn>): New support for float<->double conversions.
(vsx_xvcvdpsp): Delete, move into vsx_<VS_spdp_insn>.
(vsx_xvcvspdp): Ditto.
(vsx_xvcvuxdsp): New conversion insn.
(vsx_xvcvspsxds): Ditto.
(vsx_xvcvspuxds): Ditto.
(vsx_concat_<mode>): Generalize V2DF permute/splat operations to
include V2DI.
(vsx_set_<mode>): Ditto.
(vsx_extract_<mode>): Ditto.
(vsx_xxpermdi_<mode>): Ditto.
(vsx_splat<mode>): Ditto.
* config/rs6000/rs6000.h (VSX_VECTOR_MOVE_MODE): Delete.
(VSX_MOVE_MODE): Add TImode.
(IRA_COVER_CLASSES): Delete.
(IRA_COVER_CLASSES_PRE_VSX): New cover classes for machines
without VSX where float and altivec are different registers.
(IRA_COVER_CLASS_VSX): New cover classes for machines with VSX
where float and altivec are part of the same register class.
* config/rs6000/altivec.md (VM2): New iterator for 128-bit types,
except TImode.
(altivec_mov<mode>): Drop movti mode here.
(altivec_movti): Add movti insn, and allow GPRs, but favor altivec
registers.
2009-04-16 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_has_indirect_jump_p): New
declaration.
(rs6000_set_indirect_jump): Ditto.
* config/rs6000/rs6000.c (struct machine_function): Add
indirect_jump_p field.
(rs6000_override_options): Wrap warning messages in N_(). If
-mvsx was implicitly set, don't give a warning for -msoft-float,
just silently turn off vsx.
(rs6000_secondary_reload_inner): Don't use strict register
checking, since pseudos may still be present.
(register_move_cost): If -mdebug=cost, print out cost information.
(rs6000_memory_move_cost): Ditto.
(rs6000_has_indirect_jump_p): New function, return true if
current function has an indirect jump.
(rs6000_set_indirect_jump): New function, note that an indirect
jump has been generated.
* config/rs6000/rs6000.md (indirect_jump): Note that we've
generated an indirect jump.
(tablejump): Ditto.
(doloop_end): Do not generate decrement ctr and branch
instructions if an indirect jump has been generated.
--- gcc/doc/extend.texi (revision 146119)
+++ gcc/doc/extend.texi (revision 146798)
@@ -7094,7 +7094,7 @@ instructions, but allow the compiler to
@ -253,208 +455,6 @@
+ d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
+ return i;
+}
2009-04-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (vector_vsel<mode>): Generate the insns
directly instead of calling VSX/Altivec expanders.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Map VSX
builtins that are identical to Altivec, to the Altivec vesion.
(altivec_overloaded_builtins): Add V2DF/V2DI sel, perm support.
(altivec_resolve_overloaded_builtin): Add V2DF/V2DI support.
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Rename VSX
splat functions.
(expand_vector_set): Merge V2DF/V2DI code.
(expand_vector_extract): Ditto.
(bdesc_3arg): Add more VSX builtins.
(bdesc_2arg): Ditto.
(bdesc_1arg): Ditto.
(rs6000_expand_ternop_builtin): Require xxpermdi 3rd argument to
be 2 bit-constant, and V2DF/V2DI set to be a 1 bit-constant.
(altivec_expand_builtin): Add support for VSX overloaded builtins.
(altivec_init_builtins): Ditto.
(rs6000_common_init_builtins): Ditto.
(rs6000_init_builtins): Add V2DI types and vector long support.
(rs6000_handle_altivec_attribute): Ditto.
(rs6000_mange_type): Ditto.
* config/rs6000/vsx.md (UNSPEC_*): Add new UNSPEC constants.
(vsx_vsel<mode>): Add support for all vector types, including
Altivec types.
(vsx_ftrunc<mode>2): Emit the correct instruction.
(vsx_x<VSv>r<VSs>i): New builtin rounding mode insns.
(vsx_x<VSv>r<VSs>ic): Ditto.
(vsx_concat_<mode>): Key off of VSX memory instructions being
generated instead of the vector arithmetic unit to enable V2DI
mode.
(vsx_extract_<mode>): Ditto.
(vsx_set_<mode>): Rewrite as an unspec.
(vsx_xxpermdi2_<mode>): Rename old vsx_xxpermdi_<mode> here. Key
off of VSX memory instructions instead of arithmetic unit.
(vsx_xxpermdi_<mode>): New insn for __builtin_vsx_xxpermdi.
(vsx_splat_<mode>): Rename from vsx_splat<mode>.
(vsx_xxspltw_<mode>): Change from V4SF only to V4SF/V4SI modes.
Fix up constraints. Key off of memory instructions instead of
arithmetic instructions to allow use with V4SI.
(vsx_xxmrghw_<mode>): Ditto.
(vsx_xxmrglw_<mode>): Ditto.
(vsx_xxsldwi_<mode>): Implement vector shift double by word
immediate.
* config/rs6000/rs6000.h (VSX_BUILTIN_*): Update for current
builtins being generated.
(RS6000_BTI_unsigned_V2DI): Add vector long support.
(RS6000_BTI_bool_long): Ditto.
(RS6000_BTI_bool_V2DI): Ditto.
(unsigned_V2DI_type_node): Ditto.
(bool_long_type_node): Ditto.
(bool_V2DI_type_node): Ditto.
* config/rs6000/altivec.md (altivec_vsel<mode>): Add '*' since we
don't need the generator function now. Use VSX instruction if
-mvsx.
(altivec_vmrghw): Use VSX instruction if -mvsx.
(altivec_vmrghsf): Ditto.
(altivec_vmrglw): Ditto.
(altivec_vmrglsf): Ditto.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document that under VSX, vector double/long are available.
testsuite/
* gcc.target/powerpc/vsx-builtin-3.c: New test for VSX builtins.
2009-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_E): New iterator to add V2DImode.
(vec_init<mode>): Use VEC_E instead of VEC_C iterator, to add
V2DImode support.
(vec_set<mode>): Ditto.
(vec_extract<mode>): Ditto.
* config/rs6000/predicates.md (easy_vector_constant): Add support
for setting TImode to 0.
* config/rs6000/rs6000.opt (-mvsx-vector-memory): Delete old debug
switch that is no longer used.
(-mvsx-vector-float): Ditto.
(-mvsx-vector-double): Ditto.
(-mvsx-v4sf-altivec-regs): Ditto.
(-mreload-functions): Ditto.
(-mallow-timode): New debug switch.
* config/rs6000/rs6000.c (rs6000_ira_cover_classes): New target
hook for IRA cover classes, to know that under VSX the float and
altivec registers are part of the same register class, but before
they weren't.
(TARGET_IRA_COVER_CLASSES): Set ira cover classes target hookd.
(rs6000_hard_regno_nregs): Key off of whether VSX/Altivec memory
instructions are supported, and not whether the vector unit has
arithmetic support to enable V2DI/TI mode.
(rs6000_hard_regno_mode_ok): Ditto.
(rs6000_init_hard_regno_mode_ok): Add V2DImode, TImode support.
Drop several of the debug switches.
(rs6000_emit_move): Force TImode constants to memory if we have
either Altivec or VSX.
(rs6000_builtin_conversion): Use correct insns for V2DI<->V2DF
conversions.
(rs6000_expand_vector_init): Add V2DI support.
(rs6000_expand_vector_set): Ditto.
(avoiding_indexed_address_p): Simplify tests to say if the mode
uses VSX/Altivec memory instructions we can't eliminate reg+reg
addressing.
(rs6000_legitimize_address): Move VSX/Altivec REG+REG support
before the large integer support.
(rs6000_legitimate_address): Add support for TImode in VSX/Altivec
registers.
(rs6000_emit_move): Ditto.
(def_builtin): Change internal error message to provide more
information.
(bdesc_2arg): Add conversion builtins.
(builtin_hash_function): New function for hashing all of the types
for builtin functions.
(builtin_hash_eq): Ditto.
(builtin_function_type): Ditto.
(builtin_mode_to_type): New static for builtin argument hashing.
(builtin_hash_table): Ditto.
(rs6000_common_init_builtins): Rewrite so that types for builtin
functions are only created when we need them, and use a hash table
to store all of the different argument combinations that are
created. Add support for VSX conversion builtins.
(rs6000_preferred_reload_class): Add TImode support.
(reg_classes_cannot_change_mode_class): Be stricter about VSX and
Altivec vector types.
(rs6000_emit_vector_cond_expr): Use VSX_MOVE_MODE, not
VSX_VECTOR_MOVE_MODE.
(rs6000_handle_altivec_attribute): Allow __vector long on VSX.
* config/rs6000/vsx.md (VSX_D): New iterator for vectors with
64-bit elements.
(VSX_M): New iterator for 128 bit types for moves, except for
TImode.
(VSm, VSs, VSr): Add TImode.
(VSr4, VSr5): New mode attributes for float<->double conversion.
(VSX_SPDP): New iterator for float<->double conversion.
(VS_spdp_*): New mode attributes for float<->double conversion.
(UNSPEC_VSX_*): Rename unspec constants to remove XV from the
names. Change all users.
(vsx_mov<mode>): Drop TImode support here.
(vsx_movti): New TImode support, allow GPRs, but favor VSX
registers.
(vsx_<VS_spdp_insn>): New support for float<->double conversions.
(vsx_xvcvdpsp): Delete, move into vsx_<VS_spdp_insn>.
(vsx_xvcvspdp): Ditto.
(vsx_xvcvuxdsp): New conversion insn.
(vsx_xvcvspsxds): Ditto.
(vsx_xvcvspuxds): Ditto.
(vsx_concat_<mode>): Generalize V2DF permute/splat operations to
include V2DI.
(vsx_set_<mode>): Ditto.
(vsx_extract_<mode>): Ditto.
(vsx_xxpermdi_<mode>): Ditto.
(vsx_splat<mode>): Ditto.
* config/rs6000/rs6000.h (VSX_VECTOR_MOVE_MODE): Delete.
(VSX_MOVE_MODE): Add TImode.
(IRA_COVER_CLASSES): Delete.
(IRA_COVER_CLASSES_PRE_VSX): New cover classes for machines
without VSX where float and altivec are different registers.
(IRA_COVER_CLASS_VSX): New cover classes for machines with VSX
where float and altivec are part of the same register class.
* config/rs6000/altivec.md (VM2): New iterator for 128-bit types,
except TImode.
(altivec_mov<mode>): Drop movti mode here.
(altivec_movti): Add movti insn, and allow GPRs, but favor altivec
registers.
2009-04-16 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_has_indirect_jump_p): New
declaration.
(rs6000_set_indirect_jump): Ditto.
* config/rs6000/rs6000.c (struct machine_function): Add
indirect_jump_p field.
(rs6000_override_options): Wrap warning messages in N_(). If
-mvsx was implicitly set, don't give a warning for -msoft-float,
just silently turn off vsx.
(rs6000_secondary_reload_inner): Don't use strict register
checking, since pseudos may still be present.
(register_move_cost): If -mdebug=cost, print out cost information.
(rs6000_memory_move_cost): Ditto.
(rs6000_has_indirect_jump_p): New function, return true if
current function has an indirect jump.
(rs6000_set_indirect_jump): New function, note that an indirect
jump has been generated.
* config/rs6000/rs6000.md (indirect_jump): Note that we've
generated an indirect jump.
(tablejump): Ditto.
(doloop_end): Do not generate decrement ctr and branch
instructions if an indirect jump has been generated.
--- gcc/config/rs6000/vector.md (revision 146119)
+++ gcc/config/rs6000/vector.md (revision 146798)
@@ -39,6 +39,9 @@ (define_mode_iterator VEC_M [V16QI V8HI

223
gcc44-pr39666.patch Normal file
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@ -0,0 +1,223 @@
2009-05-05 Jakub Jelinek <jakub@redhat.com>
PR middle-end/39666
* gimplify.c (gimplify_switch_expr): If case labels cover the whole
range of the type, but default label is missing, add it with one
of the existing labels instead of adding a new label for it.
* gcc.dg/pr39666-1.c: New test.
* gcc.dg/pr39666-2.c: Likewise.
* g++.dg/warn/Wuninitialized-4.C: Likewise.
* g++.dg/warn/Wuninitialized-5.C: Likewise.
* gfortran.dg/pr39666-1.f90: Likewise.
* gfortran.dg/pr39666-2.f90: Likewise.
--- gcc/gimplify.c (revision 147135)
+++ gcc/gimplify.c (revision 147136)
@@ -1604,20 +1604,63 @@ gimplify_switch_expr (tree *expr_p, gimp
}
len = i;
+ if (!VEC_empty (tree, labels))
+ sort_case_labels (labels);
+
if (!default_case)
{
- gimple new_default;
+ tree type = TREE_TYPE (switch_expr);
/* If the switch has no default label, add one, so that we jump
- around the switch body. */
- default_case = build3 (CASE_LABEL_EXPR, void_type_node, NULL_TREE,
- NULL_TREE, create_artificial_label ());
- new_default = gimple_build_label (CASE_LABEL (default_case));
- gimplify_seq_add_stmt (&switch_body_seq, new_default);
- }
+ around the switch body. If the labels already cover the whole
+ range of type, add the default label pointing to one of the
+ existing labels. */
+ if (type == void_type_node)
+ type = TREE_TYPE (SWITCH_COND (switch_expr));
+ if (len
+ && INTEGRAL_TYPE_P (type)
+ && TYPE_MIN_VALUE (type)
+ && TYPE_MAX_VALUE (type)
+ && tree_int_cst_equal (CASE_LOW (VEC_index (tree, labels, 0)),
+ TYPE_MIN_VALUE (type)))
+ {
+ tree low, high = CASE_HIGH (VEC_index (tree, labels, len - 1));
+ if (!high)
+ high = CASE_LOW (VEC_index (tree, labels, len - 1));
+ if (tree_int_cst_equal (high, TYPE_MAX_VALUE (type)))
+ {
+ for (i = 1; i < len; i++)
+ {
+ high = CASE_LOW (VEC_index (tree, labels, i));
+ low = CASE_HIGH (VEC_index (tree, labels, i - 1));
+ if (!low)
+ low = CASE_LOW (VEC_index (tree, labels, i - 1));
+ if ((TREE_INT_CST_LOW (low) + 1
+ != TREE_INT_CST_LOW (high))
+ || (TREE_INT_CST_HIGH (low)
+ + (TREE_INT_CST_LOW (high) == 0)
+ != TREE_INT_CST_HIGH (high)))
+ break;
+ }
+ if (i == len)
+ default_case = build3 (CASE_LABEL_EXPR, void_type_node,
+ NULL_TREE, NULL_TREE,
+ CASE_LABEL (VEC_index (tree,
+ labels, 0)));
+ }
+ }
- if (!VEC_empty (tree, labels))
- sort_case_labels (labels);
+ if (!default_case)
+ {
+ gimple new_default;
+
+ default_case = build3 (CASE_LABEL_EXPR, void_type_node,
+ NULL_TREE, NULL_TREE,
+ create_artificial_label ());
+ new_default = gimple_build_label (CASE_LABEL (default_case));
+ gimplify_seq_add_stmt (&switch_body_seq, new_default);
+ }
+ }
gimple_switch = gimple_build_switch_vec (SWITCH_COND (switch_expr),
default_case, labels);
--- gcc/testsuite/gcc.dg/pr39666-1.c (revision 0)
+++ gcc/testsuite/gcc.dg/pr39666-1.c (revision 147136)
@@ -0,0 +1,22 @@
+/* PR middle-end/39666 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wuninitialized" } */
+
+int
+foo (int i)
+{
+ int j;
+ switch (i)
+ {
+ case -__INT_MAX__ - 1 ... -1:
+ j = 6;
+ break;
+ case 0:
+ j = 5;
+ break;
+ case 1 ... __INT_MAX__:
+ j = 4;
+ break;
+ }
+ return j;
+}
--- gcc/testsuite/gcc.dg/pr39666-2.c (revision 0)
+++ gcc/testsuite/gcc.dg/pr39666-2.c (revision 147136)
@@ -0,0 +1,22 @@
+/* PR middle-end/39666 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wuninitialized" } */
+
+int
+foo (int i)
+{
+ int j; /* { dg-warning "may be used uninitialized" } */
+ switch (i)
+ {
+ case -__INT_MAX__ - 1 ... -1:
+ j = 6;
+ break;
+ case 0:
+ j = 5;
+ break;
+ case 2 ... __INT_MAX__:
+ j = 4;
+ break;
+ }
+ return j;
+}
--- gcc/testsuite/g++.dg/warn/Wuninitialized-5.C (revision 0)
+++ gcc/testsuite/g++.dg/warn/Wuninitialized-5.C (revision 147136)
@@ -0,0 +1,22 @@
+// PR middle-end/39666
+// { dg-do compile }
+// { dg-options "-O2 -Wuninitialized" }
+
+int
+foo (int i)
+{
+ int j; // { dg-warning "may be used uninitialized" }
+ switch (i)
+ {
+ case -__INT_MAX__ - 1 ... -1:
+ j = 6;
+ break;
+ case 0:
+ j = 5;
+ break;
+ case 2 ... __INT_MAX__:
+ j = 4;
+ break;
+ }
+ return j;
+}
--- gcc/testsuite/g++.dg/warn/Wuninitialized-4.C (revision 0)
+++ gcc/testsuite/g++.dg/warn/Wuninitialized-4.C (revision 147136)
@@ -0,0 +1,22 @@
+// PR middle-end/39666
+// { dg-do compile }
+// { dg-options "-O2 -Wuninitialized" }
+
+int
+foo (int i)
+{
+ int j;
+ switch (i)
+ {
+ case -__INT_MAX__ - 1 ... -1:
+ j = 6;
+ break;
+ case 0:
+ j = 5;
+ break;
+ case 1 ... __INT_MAX__:
+ j = 4;
+ break;
+ }
+ return j;
+}
--- gcc/testsuite/gfortran.dg/pr39666-1.f90 (revision 0)
+++ gcc/testsuite/gfortran.dg/pr39666-1.f90 (revision 147136)
@@ -0,0 +1,14 @@
+! PR middle-end/39666
+! { dg-do compile }
+! { dg-options "-O2 -Wuninitialized" }
+
+FUNCTION f(n)
+ INTEGER, INTENT(in) :: n
+ REAL :: f
+
+ SELECT CASE (n)
+ CASE (:-1); f = -1.0
+ CASE (0); f = 0.0
+ CASE (1:); f = 1.0
+ END SELECT
+END FUNCTION
--- gcc/testsuite/gfortran.dg/pr39666-2.f90 (revision 0)
+++ gcc/testsuite/gfortran.dg/pr39666-2.f90 (revision 147136)
@@ -0,0 +1,14 @@
+! PR middle-end/39666
+! { dg-do compile }
+! { dg-options "-O2 -Wuninitialized" }
+
+FUNCTION f(n) ! { dg-warning "may be used uninitialized" }
+ INTEGER, INTENT(in) :: n
+ REAL :: f
+
+ SELECT CASE (n)
+ CASE (:-1); f = -1.0
+ CASE (0); f = 0.0
+ CASE (2:); f = 1.0
+ END SELECT
+END FUNCTION

79
gcc44-pr39903.patch
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@ -1,79 +0,0 @@
2009-04-26 H.J. Lu <hongjiu.lu@intel.com>
PR target/39903
* config/i386/i386.c (construct_container): Don't call
gen_reg_or_parallel with BLKmode for X86_64_SSE_CLASS,
X86_64_SSESF_CLASS and X86_64_SSEDF_CLASS.
PR target/39903
* gcc.dg/torture/pr39903-1.c: New.
* gcc.dg/torture/pr39903-2.c: Likewise.
--- gcc/config/i386/i386.c (revision 146817)
+++ gcc/config/i386/i386.c (working copy)
@@ -5466,7 +5466,10 @@ construct_container (enum machine_mode m
case X86_64_SSE_CLASS:
case X86_64_SSESF_CLASS:
case X86_64_SSEDF_CLASS:
- return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
+ if (mode != BLKmode)
+ return gen_reg_or_parallel (mode, orig_mode,
+ SSE_REGNO (sse_regno));
+ break;
case X86_64_X87_CLASS:
case X86_64_COMPLEX_X87_CLASS:
return gen_rtx_REG (mode, FIRST_STACK_REG);
--- gcc/testsuite/gcc.dg/torture/pr39903-1.c (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr39903-1.c (revision 0)
@@ -0,0 +1,24 @@
+/* PR target/39903 */
+/* { dg-do run } */
+/* { dg-options "-Wno-psabi" } */
+
+struct X {
+ double d;
+ double b[];
+};
+
+struct X __attribute__((noinline))
+foo (double d)
+{
+ struct X x;
+ x.d = d;
+ return x;
+}
+extern void abort (void);
+int main()
+{
+ struct X x = foo(3.0);
+ if (x.d != 3.0)
+ abort ();
+ return 0;
+}
--- gcc/testsuite/gcc.dg/torture/pr39903-2.c (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr39903-2.c (revision 0)
@@ -0,0 +1,24 @@
+/* PR target/39903 */
+/* { dg-do run } */
+/* { dg-options "-Wno-psabi" } */
+
+struct X {
+ float d;
+ float b[];
+};
+
+struct X __attribute__((noinline))
+foo (float d)
+{
+ struct X x;
+ x.d = d;
+ return x;
+}
+extern void abort (void);
+int main()
+{
+ struct X x = foo(3.0);
+ if (x.d != 3.0)
+ abort ();
+ return 0;
+}

33
gcc44-pr39942.patch Normal file
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@ -0,0 +1,33 @@
2009-05-05 Jakub Jelinek <jakub@redhat.com>
PR target/39942
* config/i386/x86-64.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Don't emit second
.p2align 3 if MAX_SKIP is smaller than 7.
* config/i386/linux.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
--- gcc/config/i386/x86-64.h.jj 2009-05-05 08:33:20.000000000 +0200
+++ gcc/config/i386/x86-64.h 2009-05-05 16:37:13.000000000 +0200
@@ -74,7 +74,9 @@ see the files COPYING3 and COPYING.RUNTI
fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
/* Make sure that we have at least 8 byte alignment if > 8 byte \
alignment is preferred. */ \
- if ((LOG) > 3 && (1 << (LOG)) > ((MAX_SKIP) + 1)) \
+ if ((LOG) > 3 \
+ && (1 << (LOG)) > ((MAX_SKIP) + 1) \
+ && (MAX_SKIP) >= 7) \
fprintf ((FILE), "\t.p2align 3\n"); \
} \
} \
--- gcc/config/i386/linux.h.jj 2009-05-05 08:33:20.000000000 +0200
+++ gcc/config/i386/linux.h 2009-05-05 16:37:13.000000000 +0200
@@ -153,7 +153,9 @@ along with GCC; see the file COPYING3.
fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
/* Make sure that we have at least 8 byte alignment if > 8 byte \
alignment is preferred. */ \
- if ((LOG) > 3 && (1 << (LOG)) > ((MAX_SKIP) + 1)) \
+ if ((LOG) > 3 \
+ && (1 << (LOG)) > ((MAX_SKIP) + 1) \
+ && (MAX_SKIP) >= 7) \
fprintf ((FILE), "\t.p2align 3\n"); \
} \
} \

68
gcc44-pr40035.patch Normal file
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@ -0,0 +1,68 @@
2009-05-05 Jakub Jelinek <jakub@redhat.com>
Ben Elliston <bje@au.ibm.com>
PR middle-end/40035
* dse.c (check_mem_read_rtx): Guard against width == -1.
* gcc.target/i386/pr40035.c: New test.
--- gcc/dse.c (revision 147137)
+++ gcc/dse.c (working copy)
@@ -2245,6 +2245,7 @@ check_mem_read_rtx (rtx *loc, void *data
if (store_info->rhs
&& store_info->group_id == -1
&& store_info->cse_base == base
+ && width != -1
&& offset >= store_info->begin
&& offset + width <= store_info->end
&& all_positions_needed_p (store_info,
--- gcc/testsuite/gcc.c-torture/compile/pr40035.c (revision 0)
+++ gcc/testsuite/gcc.c-torture/compile/pr40035.c (revision 0)
@@ -0,0 +1,46 @@
+/* PR middle-end/40035 */
+
+typedef __SIZE_TYPE__ size_t;
+
+struct kernel_param {
+ const char *name;
+ unsigned int perm;
+};
+
+extern int parse_args(const char *name,
+ char *args,
+ struct kernel_param *params,
+ unsigned num,
+ int (*unknown)(char *param, char *val));
+
+void *memmove(void *dest, const void *src, size_t count);
+size_t strlen(const char *s);
+
+static char *static_command_line;
+
+static int unknown_bootoption(char *param, char *val)
+{
+
+ if (val) {
+
+ if (val == param+strlen(param)+1)
+ val[-1] = '=';
+ else if (val == param+strlen(param)+2) {
+ val[-2] = '=';
+ memmove(val-1, val, strlen(val)+1);
+ val--;
+ }
+ }
+ return 0;
+}
+
+
+void start_kernel(void)
+{
+ char * command_line;
+ extern struct kernel_param __start___param[], __stop___param[];
+
+ parse_args("Booting kernel", static_command_line, __start___param,
+ __stop___param - __start___param,
+ &unknown_bootoption);
+}

26
gcc44-rh330771.patch
View File

@ -3,20 +3,20 @@
* Makefile.am (libgcj_tools_la_LIBADD): Add.
* Makefile.in: Regenerated.
--- libjava/Makefile.am.jj 2007-03-17 09:20:30.000000000 +0100
+++ libjava/Makefile.am 2007-10-16 15:45:14.000000000 +0200
@@ -277,6 +277,8 @@ EXTRA_libgcj_la_SOURCES = java/lang/Obje
libgcj_tools_la_SOURCES = classpath/tools/tools.zip
libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch -fno-indirect-classes -fsource-filename=$(here)/classpath/tools/all-classes.lst
--- libjava/Makefile.am.jj 2009-05-06 08:14:50.000000000 +0200
+++ libjava/Makefile.am 2009-05-06 10:26:43.000000000 +0200
@@ -314,6 +314,8 @@ libgcj_tools_la_SOURCES = classpath/tool
libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch \
-fno-bootstrap-classes -fno-indirect-classes \
-fsource-filename=$(here)/classpath/tools/all-classes.lst
+## See jv_convert_LDADD.
+libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la
libgcj_tools_la_LDFLAGS = -rpath $(toolexeclibdir) \
-version-info `grep -v '^\#' $(srcdir)/libtool-version` \
$(LIBGCJ_LD_SYMBOLIC_FUNCTIONS)
--- libjava/Makefile.in.jj 2007-07-04 21:11:11.000000000 +0200
+++ libjava/Makefile.in 2007-10-16 15:56:07.000000000 +0200
@@ -153,7 +153,6 @@ am__objects_1 = gnu/gcj/xlib/lib_gnu_awt
--- libjava/Makefile.in.jj 2009-05-06 08:14:49.000000000 +0200
+++ libjava/Makefile.in 2009-05-06 10:27:18.000000000 +0200
@@ -160,7 +160,6 @@ am__objects_1 = gnu/gcj/xlib/lib_gnu_awt
am_lib_gnu_awt_xlib_la_OBJECTS = $(am__objects_1)
lib_gnu_awt_xlib_la_OBJECTS = $(am_lib_gnu_awt_xlib_la_OBJECTS)
@XLIB_AWT_TRUE@am_lib_gnu_awt_xlib_la_rpath = -rpath $(toolexeclibdir)
@ -24,10 +24,10 @@
am_libgcj_tools_la_OBJECTS = classpath/tools/libgcj_tools_la-tools.lo
libgcj_tools_la_OBJECTS = $(am_libgcj_tools_la_OBJECTS)
@INTERPRETER_TRUE@am__DEPENDENCIES_1 = gnu/classpath/jdwp.lo \
@@ -941,6 +940,7 @@ libgcj_la_LINK = $(LIBLINK)
EXTRA_libgcj_la_SOURCES = java/lang/Object.java
libgcj_tools_la_SOURCES = classpath/tools/tools.zip
libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch -fno-indirect-classes -fsource-filename=$(here)/classpath/tools/all-classes.lst
@@ -1041,6 +1040,7 @@ libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS
-fno-bootstrap-classes -fno-indirect-classes \
-fsource-filename=$(here)/classpath/tools/all-classes.lst
+libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la
libgcj_tools_la_LDFLAGS = -rpath $(toolexeclibdir) \
-version-info `grep -v '^\#' $(srcdir)/libtool-version` \

2
sources
View File

@ -1,2 +1,2 @@
2659f09c2e43ef8b7d4406321753f1b2 fastjar-0.97.tar.gz
373986714230ac85e2d6d6e4abb107e0 gcc-4.4.0-20090427.tar.bz2
6c9913dfb6fffdf023f8de836e6b9043 gcc-4.4.0-20090506.tar.bz2