Backport 2 riscv64 specific patches
Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
parent
59ec97037b
commit
4784eb2453
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@ -0,0 +1,137 @@
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From 9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0 Mon Sep 17 00:00:00 2001
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From: Li Xu <xuli1@eswincomputing.com>
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Date: Wed, 10 May 2023 04:02:13 +0000
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Subject: [PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
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instructions satisfying REG_P(operand[1]) in -O0.
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This issue happens is because the operand1 of scalar move can be
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REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
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not insert the vsetvl instruction correctly, and the compiler crashes.
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Consider this following case:
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int16_t foo1 (void *base, size_t vl)
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{
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int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
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return maxVal;
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}
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Before this patch:
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bug.c:15:1: internal compiler error: Segmentation fault
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15 | }
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| ^
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0x145d723 crash_signal
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../.././riscv-gcc/gcc/toplev.cc:314
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0x22929dd const_csr_operand(rtx_def*, machine_mode)
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../.././riscv-gcc/gcc/config/riscv/predicates.md:44
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0x2292a21 csr_operand(rtx_def*, machine_mode)
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../.././riscv-gcc/gcc/config/riscv/predicates.md:46
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0x23dfbb0 recog_356
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../.././riscv-gcc/gcc/config/riscv/iterators.md:72
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0x23efecd recog(rtx_def*, rtx_insn*, int*)
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../.././riscv-gcc/gcc/config/riscv/iterators.md:89
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0xdddc15 recog_memoized(rtx_insn*)
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../.././riscv-gcc/gcc/recog.h:273
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After this patch:
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vsetivli zero,0,e16,m1,ta,ma
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vmv.x.s a5,v1
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gcc/ChangeLog:
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* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
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intruction replace null avl with (const_int 0).
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gcc/testsuite/ChangeLog:
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* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
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* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
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---
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gcc/config/riscv/riscv-vsetvl.cc | 5 +++
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.../riscv/rvv/base/scalar_move-10.c | 31 +++++++++++++++++++
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.../riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++
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3 files changed, 56 insertions(+)
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
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index bd45cb97e63b..0cf4bc818e2a 100644
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--- a/gcc/config/riscv/riscv-vsetvl.cc
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+++ b/gcc/config/riscv/riscv-vsetvl.cc
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@@ -618,6 +618,11 @@ static rtx
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gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info &info, rtx vl)
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{
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rtx avl = info.get_avl ();
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+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
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+ set the value of avl to (const_int 0) so that VSETVL PASS will
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+ insert vsetvl correctly.*/
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+ if (info.has_avl_no_reg ())
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+ avl = GEN_INT (0);
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rtx sew = gen_int_mode (info.get_sew (), Pmode);
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rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
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rtx ta = gen_int_mode (info.get_ta (), Pmode);
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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new file mode 100644
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index 000000000000..9760d77fb22b
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
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@@ -0,0 +1,31 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
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+/* { dg-final { check-function-bodies "**" "" } } */
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+
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+#include "riscv_vector.h"
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+
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+/*
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+** foo1:
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+** ...
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+** vsetivli\tzero,0,e16,m1,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+int16_t foo1 (void *base, size_t vl)
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+{
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+ int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
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+ return maxVal;
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+}
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+
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+/*
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+** foo2:
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+** ...
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+** vsetivli\tzero,0,e32,m1,t[au],m[au]
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+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+float foo2 (void *base, size_t vl)
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+{
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+ float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base, vl));
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+ return maxVal;
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+}
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diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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new file mode 100644
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index 000000000000..8036acd0a529
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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@@ -0,0 +1,20 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
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+/* { dg-final { check-function-bodies "**" "" } } */
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+
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+#include "riscv_vector.h"
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+
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+/*
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+** foo:
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+** ...
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+** vsetivli\tzero,0,e64,m4,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** vsetivli\tzero,0,e64,m4,t[au],m[au]
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+** vmv.x.s\t[a-x0-9]+,v[0-9]+
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+** ...
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+*/
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+int16_t foo (void *base, size_t vl)
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+{
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+ int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base, vl));
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+ return maxVal;
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+}
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--
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2.39.3
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From b81d476756a1f17617f0837761785c4b5d1d195d Mon Sep 17 00:00:00 2001
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From: Dimitar Dimitrov <dimitar@dinux.eu>
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Date: Mon, 5 Jun 2023 21:39:16 +0300
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Subject: [PATCH] riscv: Fix scope for memory model calculation
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During libgcc configure stage for riscv32-none-elf, when
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"--enable-checking=yes,rtl" has been activated, the following error
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is observed:
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during RTL pass: final
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conftest.c: In function 'main':
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conftest.c:16:1: internal compiler error: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
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16 | }
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| ^
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0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
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/mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
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0x8ea823 riscv_print_operand
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/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
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0xde84b5 output_operand(rtx_def*, int)
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
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0xde8ef8 output_asm_insn(char const*, rtx_def**)
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
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0xded33b output_asm_insn(char const*, rtx_def**)
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
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0xded33b final_scan_insn_1
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
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0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
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0xded8b7 final_1
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
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0xdee518 rest_of_handle_final
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
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0xdee518 execute
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/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318
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Fix by moving the calculation of memmodel to the cases where it is used.
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Regression tested for riscv32-none-elf. No changes in gcc.sum and
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g++.sum.
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PR target/109725
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gcc/ChangeLog:
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* config/riscv/riscv.cc (riscv_print_operand): Calculate
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memmodel only when it is valid.
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Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
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---
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gcc/config/riscv/riscv.cc | 13 +++++++++----
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1 file changed, 9 insertions(+), 4 deletions(-)
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
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index 59899268918d..01eebc83cc58 100644
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--- a/gcc/config/riscv/riscv.cc
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+++ b/gcc/config/riscv/riscv.cc
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@@ -4391,7 +4391,6 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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}
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machine_mode mode = GET_MODE (op);
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enum rtx_code code = GET_CODE (op);
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- const enum memmodel model = memmodel_base (INTVAL (op));
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switch (letter)
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{
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@@ -4528,7 +4527,8 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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fputs (GET_RTX_NAME (code), file);
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break;
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- case 'A':
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+ case 'A': {
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+ const enum memmodel model = memmodel_base (INTVAL (op));
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if (riscv_memmodel_needs_amo_acquire (model)
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&& riscv_memmodel_needs_amo_release (model))
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fputs (".aqrl", file);
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@@ -4537,18 +4537,23 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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break;
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+ }
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- case 'I':
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+ case 'I': {
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+ const enum memmodel model = memmodel_base (INTVAL (op));
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if (model == MEMMODEL_SEQ_CST)
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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break;
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+ }
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- case 'J':
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+ case 'J': {
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+ const enum memmodel model = memmodel_base (INTVAL (op));
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if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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break;
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+ }
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case 'i':
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if (code != REG)
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--
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2.39.3
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10
gcc.spec
10
gcc.spec
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@ -136,7 +136,7 @@
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Summary: Various compilers (C, C++, Objective-C, ...)
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Summary: Various compilers (C, C++, Objective-C, ...)
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Name: gcc
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Name: gcc
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Version: %{gcc_version}
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Version: %{gcc_version}
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Release: %{gcc_release}.3.riscv64%{?dist}
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Release: %{gcc_release}.4.riscv64%{?dist}
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# libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
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# libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
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# GCC Runtime Exception.
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# GCC Runtime Exception.
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License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
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License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
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@ -308,6 +308,8 @@ Patch32: ffd676ef2c9849231626a532343c7ec908558c33.patch
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Patch33: 97672bd599e32ec6d488a7532b4ad15311810a46.patch
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Patch33: 97672bd599e32ec6d488a7532b4ad15311810a46.patch
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Patch34: 93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch
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Patch34: 93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch
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Patch35: a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch
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Patch35: a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch
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Patch36: 9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0.patch
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Patch37: b81d476756a1f17617f0837761785c4b5d1d195d.patch
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# On ARM EABI systems, we do want -gnueabi to be part of the
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# On ARM EABI systems, we do want -gnueabi to be part of the
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# target triple.
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# target triple.
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@ -898,6 +900,8 @@ touch -r isl-0.24/m4/ax_prog_cxx_for_build.m4 isl-0.24/m4/ax_prog_cc_for_build.m
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%patch -P33 -p1 -b .97672bd599e32ec6d488a7532b4ad15311810a46~
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%patch -P33 -p1 -b .97672bd599e32ec6d488a7532b4ad15311810a46~
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%patch -P34 -p1 -b .93c4226585cc53fd86dfa3ca2d70d5b417d960b3~
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%patch -P34 -p1 -b .93c4226585cc53fd86dfa3ca2d70d5b417d960b3~
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%patch -P35 -p1 -b .a8a7ba2e295908f40bb6f3b0965c298fb8228e22~
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%patch -P35 -p1 -b .a8a7ba2e295908f40bb6f3b0965c298fb8228e22~
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%patch -P36 -p1 -b .9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0~
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%patch -P37 -p1 -b .b81d476756a1f17617f0837761785c4b5d1d195d~
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%if 0%{?rhel} >= 9
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%if 0%{?rhel} >= 9
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%patch -P100 -p1 -b .fortran-fdec-duplicates~
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%patch -P100 -p1 -b .fortran-fdec-duplicates~
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@ -3499,6 +3503,10 @@ end
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%endif
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%endif
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%changelog
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%changelog
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* Tue Sep 05 2023 David Abdurachmanov <davidlt@rivosinc.com> 13.2.1-1.4.riscv64
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- Backport riscv64 specific patches (2 in total) from
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refs/heads/releases/gcc-13
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* Fri Aug 25 2023 David Abdurachmanov <davidlt@rivosinc.com> 13.2.1-1.1.riscv64
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* Fri Aug 25 2023 David Abdurachmanov <davidlt@rivosinc.com> 13.2.1-1.1.riscv64
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- Backport riscv64 specific patches (16 in total) from
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- Backport riscv64 specific patches (16 in total) from
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refs/heads/releases/gcc-13
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refs/heads/releases/gcc-13
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