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Backport 2 riscv64 specific patches

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Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
David Abdurachmanov 2023-09-05 14:19:41 +03:00
parent 59ec97037b
commit 4784eb2453
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
3 changed files with 249 additions and 1 deletions
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137
9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0.patch Normal file
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@ -0,0 +1,137 @@
From 9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0 Mon Sep 17 00:00:00 2001
From: Li Xu <xuli1@eswincomputing.com>
Date: Wed, 10 May 2023 04:02:13 +0000
Subject: [PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1]) in -O0.
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
return maxVal;
}
Before this patch:
bug.c:15:1: internal compiler error: Segmentation fault
15 | }
| ^
0x145d723 crash_signal
../.././riscv-gcc/gcc/toplev.cc:314
0x22929dd const_csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:44
0x2292a21 csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:46
0x23dfbb0 recog_356
../.././riscv-gcc/gcc/config/riscv/iterators.md:72
0x23efecd recog(rtx_def*, rtx_insn*, int*)
../.././riscv-gcc/gcc/config/riscv/iterators.md:89
0xdddc15 recog_memoized(rtx_insn*)
../.././riscv-gcc/gcc/recog.h:273
After this patch:
vsetivli zero,0,e16,m1,ta,ma
vmv.x.s a5,v1
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 5 +++
.../riscv/rvv/base/scalar_move-10.c | 31 +++++++++++++++++++
.../riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index bd45cb97e63b..0cf4bc818e2a 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -618,6 +618,11 @@ static rtx
gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info &info, rtx vl)
{
rtx avl = info.get_avl ();
+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
+ set the value of avl to (const_int 0) so that VSETVL PASS will
+ insert vsetvl correctly.*/
+ if (info.has_avl_no_reg ())
+ avl = GEN_INT (0);
rtx sew = gen_int_mode (info.get_sew (), Pmode);
rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
rtx ta = gen_int_mode (info.get_ta (), Pmode);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
new file mode 100644
index 000000000000..9760d77fb22b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo1:
+** ...
+** vsetivli\tzero,0,e16,m1,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo1 (void *base, size_t vl)
+{
+ int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
+ return maxVal;
+}
+
+/*
+** foo2:
+** ...
+** vsetivli\tzero,0,e32,m1,t[au],m[au]
+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
+** ...
+*/
+float foo2 (void *base, size_t vl)
+{
+ float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base, vl));
+ return maxVal;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
new file mode 100644
index 000000000000..8036acd0a529
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo:
+** ...
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo (void *base, size_t vl)
+{
+ int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base, vl));
+ return maxVal;
+}
--
2.39.3

103
b81d476756a1f17617f0837761785c4b5d1d195d.patch Normal file
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@ -0,0 +1,103 @@
From b81d476756a1f17617f0837761785c4b5d1d195d Mon Sep 17 00:00:00 2001
From: Dimitar Dimitrov <dimitar@dinux.eu>
Date: Mon, 5 Jun 2023 21:39:16 +0300
Subject: [PATCH] riscv: Fix scope for memory model calculation
During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:
during RTL pass: final
conftest.c: In function 'main':
conftest.c:16:1: internal compiler error: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
16 | }
| ^
0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
0x8ea823 riscv_print_operand
/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
0xde84b5 output_operand(rtx_def*, int)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
0xde8ef8 output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
0xded33b output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
0xded33b final_scan_insn_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
0xded8b7 final_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
0xdee518 rest_of_handle_final
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
0xdee518 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318
Fix by moving the calculation of memmodel to the cases where it is used.
Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.
PR target/109725
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Calculate
memmodel only when it is valid.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
gcc/config/riscv/riscv.cc | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 59899268918d..01eebc83cc58 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4391,7 +4391,6 @@ riscv_print_operand (FILE *file, rtx op, int letter)
}
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
- const enum memmodel model = memmodel_base (INTVAL (op));
switch (letter)
{
@@ -4528,7 +4527,8 @@ riscv_print_operand (FILE *file, rtx op, int letter)
fputs (GET_RTX_NAME (code), file);
break;
- case 'A':
+ case 'A': {
+ const enum memmodel model = memmodel_base (INTVAL (op));
if (riscv_memmodel_needs_amo_acquire (model)
&& riscv_memmodel_needs_amo_release (model))
fputs (".aqrl", file);
@@ -4537,18 +4537,23 @@ riscv_print_operand (FILE *file, rtx op, int letter)
else if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
break;
+ }
- case 'I':
+ case 'I': {
+ const enum memmodel model = memmodel_base (INTVAL (op));
if (model == MEMMODEL_SEQ_CST)
fputs (".aqrl", file);
else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
break;
+ }
- case 'J':
+ case 'J': {
+ const enum memmodel model = memmodel_base (INTVAL (op));
if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
break;
+ }
case 'i':
if (code != REG)
--
2.39.3

10
gcc.spec
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@ -136,7 +136,7 @@
Summary: Various compilers (C, C++, Objective-C, ...)
Name: gcc
Version: %{gcc_version}
Release: %{gcc_release}.3.riscv64%{?dist}
Release: %{gcc_release}.4.riscv64%{?dist}
# libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
# GCC Runtime Exception.
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
@ -308,6 +308,8 @@ Patch32: ffd676ef2c9849231626a532343c7ec908558c33.patch
Patch33: 97672bd599e32ec6d488a7532b4ad15311810a46.patch
Patch34: 93c4226585cc53fd86dfa3ca2d70d5b417d960b3.patch
Patch35: a8a7ba2e295908f40bb6f3b0965c298fb8228e22.patch
Patch36: 9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0.patch
Patch37: b81d476756a1f17617f0837761785c4b5d1d195d.patch
# On ARM EABI systems, we do want -gnueabi to be part of the
# target triple.
@ -898,6 +900,8 @@ touch -r isl-0.24/m4/ax_prog_cxx_for_build.m4 isl-0.24/m4/ax_prog_cc_for_build.m
%patch -P33 -p1 -b .97672bd599e32ec6d488a7532b4ad15311810a46~
%patch -P34 -p1 -b .93c4226585cc53fd86dfa3ca2d70d5b417d960b3~
%patch -P35 -p1 -b .a8a7ba2e295908f40bb6f3b0965c298fb8228e22~
%patch -P36 -p1 -b .9f8d1d448e6c10fbad3bb41f4d7322fac8df4cd0~
%patch -P37 -p1 -b .b81d476756a1f17617f0837761785c4b5d1d195d~
%if 0%{?rhel} >= 9
%patch -P100 -p1 -b .fortran-fdec-duplicates~
@ -3499,6 +3503,10 @@ end
%endif
%changelog
* Tue Sep 05 2023 David Abdurachmanov <davidlt@rivosinc.com> 13.2.1-1.4.riscv64
- Backport riscv64 specific patches (2 in total) from
refs/heads/releases/gcc-13
* Fri Aug 25 2023 David Abdurachmanov <davidlt@rivosinc.com> 13.2.1-1.1.riscv64
- Backport riscv64 specific patches (16 in total) from
refs/heads/releases/gcc-13