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Re-enable D on riscv64

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Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
This commit is contained in:
David Abdurachmanov 2019-01-25 15:06:53 +01:00
parent 7aa8980a44
commit 3b8a9cac14
Signed by: davidlt
GPG Key ID: 7108702C938B13C1
2 changed files with 174 additions and 1 deletions
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2
gcc.spec
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@ -33,7 +33,7 @@
%else
%global build_go 0
%endif
%ifarch %{ix86} x86_64 %{arm} %{mips}
%ifarch %{ix86} x86_64 %{arm} %{mips} riscv64
%global build_d 1
%else
%global build_d 0

173
libphobos-enable-riscv.patch
View File

@ -11,3 +11,176 @@ index 2b2a97468..f8775b712 100644
*)
UNSUPPORTED=1
;;
diff --git a/libphobos/libdruntime/core/atomic.d b/libphobos/libdruntime/core/atomic.d
index 0b39cddb6..5a6c4b854 100644
--- a/libphobos/libdruntime/core/atomic.d
+++ b/libphobos/libdruntime/core/atomic.d
@@ -1353,7 +1353,7 @@ else version (GNU)
private bool casImpl(T,V1,V2)( shared(T)* here, V1 ifThis, V2 writeThis ) pure nothrow @nogc @trusted
{
- static assert(GNU_Have_Atomics, "cas() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "cas() not supported on this architecture");
bool res = void;
static if (T.sizeof == byte.sizeof)
@@ -1406,7 +1406,7 @@ else version (GNU)
{
static assert(ms != MemoryOrder.rel, "Invalid MemoryOrder for atomicLoad");
static assert(__traits(isPOD, T), "argument to atomicLoad() must be POD");
- static assert(GNU_Have_Atomics, "atomicLoad() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "atomicLoad() not supported on this architecture");
static if (T.sizeof == ubyte.sizeof)
{
@@ -1444,7 +1444,7 @@ else version (GNU)
{
static assert(ms != MemoryOrder.acq, "Invalid MemoryOrder for atomicStore");
static assert(__traits(isPOD, T), "argument to atomicLoad() must be POD");
- static assert(GNU_Have_Atomics, "atomicStore() not supported on this architecture");
+ static assert(GNU_Have_Atomics || GNU_Have_LibAtomic, "atomicStore() not supported on this architecture");
static if (T.sizeof == ubyte.sizeof)
{
diff --git a/libphobos/src/std/experimental/allocator/building_blocks/region.d b/libphobos/src/std/experimental/allocator/building_blocks/region.d
index 80157aee7..ad90d17df 100644
--- a/libphobos/src/std/experimental/allocator/building_blocks/region.d
+++ b/libphobos/src/std/experimental/allocator/building_blocks/region.d
@@ -390,7 +390,8 @@ struct InSituRegion(size_t size, size_t minAlign = platformAlignment)
else version (PPC) enum growDownwards = Yes.growDownwards;
else version (PPC64) enum growDownwards = Yes.growDownwards;
else version (MIPS32) enum growDownwards = Yes.growDownwards;
- else version (MIPS64) enum growDownwards = Yes.growDownwards;
+ else version (RISCV32) enum growDownwards = Yes.growDownwards;
+ else version (RISCV64) enum growDownwards = Yes.growDownwards;
else version (SPARC) enum growDownwards = Yes.growDownwards;
else version (SystemZ) enum growDownwards = Yes.growDownwards;
else static assert(0, "Dunno how the stack grows on this architecture.");
diff --git a/libphobos/src/std/math.d b/libphobos/src/std/math.d
index 7bb4d7c23..0cf0c311e 100644
--- a/libphobos/src/std/math.d
+++ b/libphobos/src/std/math.d
@@ -160,6 +160,8 @@ version (MIPS32) version = MIPS_Any;
version (MIPS64) version = MIPS_Any;
version (AArch64) version = ARM_Any;
version (ARM) version = ARM_Any;
+version (RISCV32) version = RISCV_Any;
+version (RISCV64) version = RISCV_Any;
version (D_InlineAsm_X86)
{
@@ -4654,6 +4656,7 @@ private:
// The Pentium SSE2 status register is 32 bits.
// The ARM and PowerPC FPSCR is a 32-bit register.
// The SPARC FSR is a 32bit register (64 bits for SPARC 7 & 8, but high bits are uninteresting).
+ // The RISC-V (32 & 64 bit) are 32-bit register.
uint flags;
version (CRuntime_Microsoft)
@@ -4725,6 +4728,15 @@ private:
return result;
}
}
+ else version (RISCV_Any)
+ {
+ uint result = void;
+ asm pure nothrow @nogc
+ {
+ "frflags %0" : "=r" (result);
+ }
+ return result;
+ }
else
assert(0, "Not yet supported");
}
@@ -4799,6 +4811,15 @@ private:
}
}
}
+ else version (RISCV_Any)
+ {
+ uint oldValues = void;
+ uint newValues = 0x0;
+ asm pure nothrow @nogc
+ {
+ "fsflags %0 %1" : "=r" (oldValues) : "r" (newValues);
+ }
+ }
else
assert(0, "Not yet supported");
}
@@ -4968,6 +4989,10 @@ else version (PPC_Any)
{
version = IeeeFlagsSupport;
}
+else version (RISCV_Any)
+{
+ version = IeeeFlagsSupport;
+}
else version (MIPS_Any)
{
version = IeeeFlagsSupport;
@@ -5162,6 +5187,21 @@ struct FloatingPointControl
| inexactException,
}
}
+ else version (RISCV_Any)
+ {
+ enum : ExceptionMask
+ {
+ inexactException = 0x01,
+ divByZeroException = 0x02,
+ underflowException = 0x04,
+ overflowException = 0x08,
+ invalidException = 0x10,
+ severeExceptions = overflowException | divByZeroException
+ | invalidException,
+ allExceptions = severeExceptions | underflowException
+ | inexactException,
+ }
+ }
else version (SPARC64)
{
enum : ExceptionMask
@@ -5292,6 +5332,10 @@ private:
{
alias ControlState = uint;
}
+ else version (RISCV_Any)
+ {
+ alias ControlState = uint;
+ }
else version (SPARC64)
{
alias ControlState = ulong;
@@ -5359,6 +5403,15 @@ private:
}
return cont;
}
+ else version (RISCV_Any)
+ {
+ ControlState cont;
+ asm pure nothrow @nogc
+ {
+ "frcsr %0" : "=r" (cont);
+ }
+ return cont;
+ }
else
assert(0, "Not yet supported");
}
@@ -5444,6 +5497,14 @@ private:
}
}
}
+ else version (RISCV_Any)
+ {
+ uint oldState = void;
+ asm pure nothrow @nogc
+ {
+ "fscsr %0, %1;" : "=r" (oldState) : "r" (newState);
+ }
+ }
else
assert(0, "Not yet supported");
}