diff --git a/.cvsignore b/.cvsignore index 5d96dbf..c43a214 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1 +1 @@ -gcc-4.1.2-20070723.tar.bz2 +gcc-4.1.2-20070816.tar.bz2 diff --git a/gcc41-pr22244.patch b/gcc41-pr22244.patch new file mode 100644 index 0000000..b7e037e --- /dev/null +++ b/gcc41-pr22244.patch @@ -0,0 +1,63 @@ +2007-08-14 Jakub Jelinek + + PR fortran/22244 + * Make-lang.in (fortran/trans-types.o): Depend on $(FLAGS_H). + * trans-types.c: Include flags.h. + (gfc_get_nodesc_array_type): Add TYPE_DECL TYPE_NAME with + correct bounds and dimensions for packed arrays. + +--- gcc/fortran/Make-lang.in (revision 127395) ++++ gcc/fortran/Make-lang.in (working copy) +@@ -292,7 +292,7 @@ fortran/trans-decl.o: $(GFORTRAN_TRANS_D + cgraph.h $(TARGET_H) function.h $(FLAGS_H) $(RTL_H) tree-gimple.h \ + tree-dump.h + fortran/trans-types.o: $(GFORTRAN_TRANS_DEPS) gt-fortran-trans-types.h \ +- real.h toplev.h $(TARGET_H) ++ real.h toplev.h $(TARGET_H) $(FLAGS_H) + fortran/trans-const.o: $(GFORTRAN_TRANS_DEPS) + fortran/trans-expr.o: $(GFORTRAN_TRANS_DEPS) fortran/dependency.h + fortran/trans-stmt.o: $(GFORTRAN_TRANS_DEPS) fortran/dependency.h +--- gcc/fortran/trans-types.c (revision 127395) ++++ gcc/fortran/trans-types.c (working copy) +@@ -35,6 +35,7 @@ Software Foundation, 51 Franklin Street, + #include "trans-types.h" + #include "trans-const.h" + #include "real.h" ++#include "flags.h" + + + #if (GFC_MAX_DIMENSIONS < 10) +@@ -1005,7 +1006,7 @@ gfc_get_nodesc_array_type (tree etype, g + { + /* Fill in the stride and bound components of the type. */ + if (known_stride) +- tmp = gfc_conv_mpz_to_tree (stride, gfc_index_integer_kind); ++ tmp = gfc_conv_mpz_to_tree (stride, gfc_index_integer_kind); + else + tmp = NULL_TREE; + GFC_TYPE_ARRAY_STRIDE (type, n) = tmp; +@@ -1103,6 +1104,24 @@ gfc_get_nodesc_array_type (tree etype, g + mpz_clear (stride); + mpz_clear (delta); + ++ /* In debug info represent packed arrays as multi-dimensional ++ if they have rank > 1 and with proper bounds, instead of flat ++ arrays. */ ++ if (known_stride && write_symbols != NO_DEBUG) ++ { ++ tree gtype = etype, rtype, type_decl; ++ ++ for (n = as->rank - 1; n >= 0; n--) ++ { ++ rtype = build_range_type (gfc_array_index_type, ++ GFC_TYPE_ARRAY_LBOUND (type, n), ++ GFC_TYPE_ARRAY_UBOUND (type, n)); ++ gtype = build_array_type (gtype, rtype); ++ } ++ TYPE_NAME (type) = type_decl = build_decl (TYPE_DECL, NULL, gtype); ++ DECL_ORIGINAL_TYPE (type_decl) = gtype; ++ } ++ + if (packed < 3 || !known_stride) + { + /* For dummy arrays and automatic (heap allocated) arrays we diff --git a/gcc41-pr32678.patch b/gcc41-pr32678.patch new file mode 100644 index 0000000..61692bb --- /dev/null +++ b/gcc41-pr32678.patch @@ -0,0 +1,63 @@ +2007-07-21 Jerry DeLisle + + PR libgfortran/32678 + * io/transfer.c (formatted_transfer_scalar): Fix off by one error in + calculation of pos and skips. Don't allow pending_spaces to go + negative. + + PR fortran/32678 + * gfortran.dg/fmt_t_5.f90: New test. + +--- libgfortran/io/transfer.c (revision 126821) ++++ libgfortran/io/transfer.c (revision 126823) +@@ -893,9 +893,9 @@ formatted_transfer_scalar (st_parameter_ + case FMT_TR: + consume_data_flag = 0 ; + +- pos = bytes_used + f->u.n + dtp->u.p.skips; +- dtp->u.p.skips = f->u.n + dtp->u.p.skips; +- dtp->u.p.pending_spaces = pos - dtp->u.p.max_pos; ++ dtp->u.p.skips += f->u.n; ++ pos = bytes_used + dtp->u.p.skips - 1; ++ dtp->u.p.pending_spaces = pos - dtp->u.p.max_pos + 1; + + /* Writes occur just before the switch on f->format, above, so + that trailing blanks are suppressed, unless we are doing a +@@ -922,8 +922,6 @@ formatted_transfer_scalar (st_parameter_ + if (bytes_used == 0) + { + dtp->u.p.pending_spaces -= f->u.n; +- dtp->u.p.pending_spaces = dtp->u.p.pending_spaces < 0 ? 0 +- : dtp->u.p.pending_spaces; + dtp->u.p.skips -= f->u.n; + dtp->u.p.skips = dtp->u.p.skips < 0 ? 0 : dtp->u.p.skips; + } +@@ -945,6 +943,8 @@ formatted_transfer_scalar (st_parameter_ + dtp->u.p.skips = dtp->u.p.skips + pos - bytes_used; + dtp->u.p.pending_spaces = dtp->u.p.pending_spaces + + pos - dtp->u.p.max_pos; ++ dtp->u.p.pending_spaces = dtp->u.p.pending_spaces < 0 ++ ? 0 : dtp->u.p.pending_spaces; + + if (dtp->u.p.skips == 0) + break; +--- gcc/testsuite/gfortran.dg/fmt_t_5.f90 (revision 126821) ++++ gcc/testsuite/gfortran.dg/fmt_t_5.f90 (revision 126823) +@@ -0,0 +1,17 @@ ++! { dg-do run } ++! PR32678 GFortan works incorrectly when writing with FORMAT Tx ++! Before patch, NULLs were inserted in output. ++! Test case from reporter enhanced to detect this problem. ++ character(25) :: output ++ character(1) :: c ++ output = "" ++ open (unit=10, file="pr32678testfile", status="replace") ++ write (10,10) '12','a','b' ++ close (10, status="keep") ++ open (unit=10, file="pr32678testfile") ++ read(10,20) output(1:21) ++ if (output(1:21).ne."ab x") call abort ++ close (10, status="delete") ++ 10 format (a2,t1,a1,t2,a1,t20,' x') ++ 20 format (a21) ++ end diff --git a/gcc41-pr32992.patch b/gcc41-pr32992.patch new file mode 100644 index 0000000..efdf41b --- /dev/null +++ b/gcc41-pr32992.patch @@ -0,0 +1,72 @@ +2007-08-13 Jakub Jelinek + + PR c++/32992 + * typeck.c (check_return_expr): Don't NRV optimize vars in + anonymous unions. + * decl.c (finish_function): Comment fix. + + * g++.dg/opt/nrv14.C: New test. + +--- gcc/cp/typeck.c.jj 2007-08-13 15:10:19.000000000 +0200 ++++ gcc/cp/typeck.c 2007-08-13 18:00:15.000000000 +0200 +@@ -6446,6 +6446,7 @@ check_return_expr (tree retval, bool *no + && TREE_CODE (retval) == VAR_DECL + && DECL_CONTEXT (retval) == current_function_decl + && ! TREE_STATIC (retval) ++ && ! DECL_HAS_VALUE_EXPR_P (retval) + && (DECL_ALIGN (retval) + >= DECL_ALIGN (DECL_RESULT (current_function_decl))) + && same_type_p ((TYPE_MAIN_VARIANT +--- gcc/cp/decl.c.jj 2007-08-13 15:10:19.000000000 +0200 ++++ gcc/cp/decl.c 2007-08-13 18:09:33.000000000 +0200 +@@ -11566,7 +11566,7 @@ finish_function (int flags) + gcc_assert (stmts_are_full_exprs_p ()); + + /* Set up the named return value optimization, if we can. Candidate +- variables are selected in check_return_value. */ ++ variables are selected in check_return_expr. */ + if (current_function_return_value) + { + tree r = current_function_return_value; +--- gcc/testsuite/g++.dg/opt/nrv14.C.jj 2007-08-13 18:07:09.000000000 +0200 ++++ gcc/testsuite/g++.dg/opt/nrv14.C 2007-08-13 18:07:46.000000000 +0200 +@@ -0,0 +1,39 @@ ++// PR c++/32992 ++// { dg-do run } ++// { dg-options "-O2" } ++ ++extern "C" void abort (void); ++ ++struct A ++{ ++ long int a1; ++ long int a2; ++ long int a3; ++}; ++ ++struct B ++{ ++ long int f[3]; ++ operator A () ++ { ++ union ++ { ++ long int t[3]; ++ A a; ++ }; ++ for (int i = 0; i < 3; i++) ++ t[i] = f[i]; ++ return a; ++ } ++}; ++ ++int ++main () ++{ ++ B b = { {1, 3, 5} }; ++ A a = b; ++ ++ if (a.a1 != b.f[0] || a.a2 != b.f[1] || a.a3 != b.f[2]) ++ abort (); ++ return 0; ++} diff --git a/gcc41-sparc-niagara.patch b/gcc41-sparc-niagara.patch new file mode 100644 index 0000000..c9e61ba --- /dev/null +++ b/gcc41-sparc-niagara.patch @@ -0,0 +1,519 @@ +2006-03-02 David S. Miller + + Sun Niagara specific optimizations. + * config.gcc: Recognize niagara as target. + * config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Mention Niagara. + (TARGET_CPU_niagara): Define. + (CPP_CPU64_DEFAULT_SPEC): Define __sparc_v9__ for Niagara. + (ASM_CPU64_DEFAULT_SPEC): Pass -Av9b for Niagara. + (CPP_CPU_SPEC): Handle -mcpu=niagara. + (ASM_CPU_SPEC): Likewise. + (PROCESSOR_NIAGARA): New enum entry. + (REGISTER_MOVE_COST): Handle Niagara. + (BRANCH_COST, PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): Likewise. + * config/sparc/sparc.c (niagara_costs): New processor_costs entry. + (sparc_override_options): Recognize "niagara", set appropriate + default MASK_* values for it, and align functions to 32-bytes + by default just like ULTRASPARC/ULTRASPARC3. + (sparc_initialize_trampoline): Handle niagara like ultrasparc. + (sparc64_initialize_trampoline): Likewise. + (sparc_use_sched_lookahead): Use zero for niagara. + (sparc_issue_rate): Use one for niagara. + * config/sparc/niagara.md: New file. + * config/sparc/sparc.md: Include it. + * config/sparc/sol2-bi.h (CPP_CPU64_DEFAULT_SPEC, + ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC): Set appropriately + when default cpu is niagara. + (CPP_CPU_SPEC): Handle -mcpu=niagara. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sol2.h (ASM_CPU_DEFAULT_SPEC): Set appropriately + when default cpu is niagara. + (ASM_CPU_SPEC): Handle -mcpu=niagara. + * config/sparc/linux64.h: Handle a default of TARGET_CPU_niagara + just like v9/ultrasparc/ultrasparc3. + * doc/invoke.texi: Add documentation for "niagara" and improve + existing documentation for ultrasparc variants. + +--- gcc/doc/invoke.texi (revision 111647) ++++ gcc/doc/invoke.texi (revision 111648) +@@ -12268,8 +12268,8 @@ Set the instruction set, register set, a + for machine type @var{cpu_type}. Supported values for @var{cpu_type} are + @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite}, + @samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x}, +-@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and +-@samp{ultrasparc3}. ++@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, ++@samp{ultrasparc3}, and @samp{niagara}. + + Default instruction scheduling parameters are used for values that select + an architecture and not an implementation. These are @samp{v7}, @samp{v8}, +@@ -12283,7 +12283,7 @@ implementations. + v8: supersparc, hypersparc + sparclite: f930, f934, sparclite86x + sparclet: tsc701 +- v9: ultrasparc, ultrasparc3 ++ v9: ultrasparc, ultrasparc3, niagara + @end smallexample + + By default (unless configured otherwise), GCC generates code for the V7 +@@ -12317,9 +12317,11 @@ With @option{-mcpu=v9}, GCC generates co + architecture. This adds 64-bit integer and floating-point move instructions, + 3 additional floating-point condition code registers and conditional move + instructions. With @option{-mcpu=ultrasparc}, the compiler additionally +-optimizes it for the Sun UltraSPARC I/II chips. With ++optimizes it for the Sun UltraSPARC I/II/IIi chips. With + @option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the +-Sun UltraSPARC III chip. ++Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With ++@option{-mcpu=niagara}, the compiler additionally optimizes it for ++Sun UltraSPARC T1 chips. + + @item -mtune=@var{cpu_type} + @opindex mtune +@@ -12331,8 +12333,8 @@ The same values for @option{-mcpu=@var{c + @option{-mtune=@var{cpu_type}}, but the only useful values are those + that select a particular cpu implementation. Those are @samp{cypress}, + @samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934}, +-@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and +-@samp{ultrasparc3}. ++@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, ++@samp{ultrasparc3}, and @samp{niagara}. + + @item -mv8plus + @itemx -mno-v8plus +--- gcc/config.gcc (revision 111647) ++++ gcc/config.gcc (revision 111648) +@@ -2830,7 +2830,7 @@ case "${target}" in + "" | sparc | sparcv9 | sparc64 | sparc86x \ + | v7 | cypress | v8 | supersparc | sparclite | f930 \ + | f934 | hypersparc | sparclite86x | sparclet | tsc701 \ +- | v9 | ultrasparc | ultrasparc3) ++ | v9 | ultrasparc | ultrasparc3 | niagara) + # OK + ;; + *) +--- gcc/config/sparc/niagara.md (revision 0) ++++ gcc/config/sparc/niagara.md (revision 111648) +@@ -0,0 +1,119 @@ ++;; Scheduling description for Niagara. ++;; Copyright (C) 2006 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 2, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING. If not, write to ++;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ++;; Boston, MA 02110-1301, USA. ++ ++;; Niagara is a single-issue processor. ++ ++(define_automaton "niagara_0") ++ ++(define_cpu_unit "niag_pipe" "niagara_0") ++ ++(define_insn_reservation "niag_5cycle" 5 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "multi,flushw,iflush,trap")) ++ "niag_pipe*5") ++ ++(define_insn_reservation "niag_4cycle" 4 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "savew")) ++ "niag_pipe*4") ++ ++/* Most basic operations are single-cycle. */ ++(define_insn_reservation "niag_ialu" 1 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "ialu,shift,compare,cmove")) ++ "niag_pipe") ++ ++(define_insn_reservation "niag_imul" 11 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "imul")) ++ "niag_pipe*11") ++ ++(define_insn_reservation "niag_idiv" 72 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "idiv")) ++ "niag_pipe*72") ++ ++(define_insn_reservation "niag_branch" 3 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) ++ "niag_pipe*3") ++ ++(define_insn_reservation "niag_3cycle_load" 3 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "load")) ++ "niag_pipe*3") ++ ++(define_insn_reservation "niag_9cycle_load" 9 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpload")) ++ "niag_pipe*9") ++ ++(define_insn_reservation "niag_1cycle_store" 1 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "store")) ++ "niag_pipe") ++ ++(define_insn_reservation "niag_8cycle_store" 8 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpstore")) ++ "niag_pipe*8") ++ ++/* Things incorrectly modelled here: ++ * FPADD{s,d}: 26 cycles ++ * FPSUB{s,d}: 26 cycles ++ * FABSD: 26 cycles ++ * F{s,d}TO{s,d}: 26 cycles ++ * F{s,d}TO{i,x}: 26 cycles ++ * FSMULD: 29 cycles ++ */ ++(define_insn_reservation "niag_fmov" 8 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpmove,fpcmove,fpcrmove")) ++ "niag_pipe*8") ++ ++(define_insn_reservation "niag_fpcmp" 26 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpcmp")) ++ "niag_pipe*26") ++ ++(define_insn_reservation "niag_fmult" 29 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpmul")) ++ "niag_pipe*29") ++ ++(define_insn_reservation "niag_fdivs" 54 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpdivs")) ++ "niag_pipe*54") ++ ++(define_insn_reservation "niag_fdivd" 83 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fpdivd")) ++ "niag_pipe*83") ++ ++/* Things incorrectly modelled here: ++ * FPADD{16,32}: 10 cycles ++ * FPSUB{16,32}: 10 cycles ++ * FALIGNDATA: 10 cycles ++ */ ++(define_insn_reservation "niag_vis" 8 ++ (and (eq_attr "cpu" "niagara") ++ (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist")) ++ "niag_pipe*8") +--- gcc/config/sparc/sparc.md (revision 111647) ++++ gcc/config/sparc/sparc.md (revision 111648) +@@ -94,7 +94,8 @@ (define_attr "cpu" + sparclet,tsc701, + v9, + ultrasparc, +- ultrasparc3" ++ ultrasparc3, ++ niagara" + (const (symbol_ref "sparc_cpu_attr"))) + + ;; Attribute for the instruction set. +@@ -315,6 +316,7 @@ (define_delay (eq_attr "type" "return") + (include "sparclet.md") + (include "ultra1_2.md") + (include "ultra3.md") ++(include "niagara.md") + + + ;; Operand and operator predicates. +--- gcc/config/sparc/sparc.c (revision 111647) ++++ gcc/config/sparc/sparc.c (revision 111648) +@@ -197,6 +197,30 @@ struct processor_costs ultrasparc3_costs + 0, /* shift penalty */ + }; + ++static const ++struct processor_costs niagara_costs = { ++ COSTS_N_INSNS (3), /* int load */ ++ COSTS_N_INSNS (3), /* int signed load */ ++ COSTS_N_INSNS (3), /* int zeroed load */ ++ COSTS_N_INSNS (9), /* float load */ ++ COSTS_N_INSNS (8), /* fmov, fneg, fabs */ ++ COSTS_N_INSNS (8), /* fadd, fsub */ ++ COSTS_N_INSNS (26), /* fcmp */ ++ COSTS_N_INSNS (8), /* fmov, fmovr */ ++ COSTS_N_INSNS (29), /* fmul */ ++ COSTS_N_INSNS (54), /* fdivs */ ++ COSTS_N_INSNS (83), /* fdivd */ ++ COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */ ++ COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */ ++ COSTS_N_INSNS (11), /* imul */ ++ COSTS_N_INSNS (11), /* imulX */ ++ 0, /* imul bit factor */ ++ COSTS_N_INSNS (72), /* idiv */ ++ COSTS_N_INSNS (72), /* idivX */ ++ COSTS_N_INSNS (1), /* movcc/movr */ ++ 0, /* shift penalty */ ++}; ++ + const struct processor_costs *sparc_costs = &cypress_costs; + + #ifdef HAVE_AS_RELAX_OPTION +@@ -597,6 +621,7 @@ sparc_override_options (void) + { TARGET_CPU_v9, "v9" }, + { TARGET_CPU_ultrasparc, "ultrasparc" }, + { TARGET_CPU_ultrasparc3, "ultrasparc3" }, ++ { TARGET_CPU_niagara, "niagara" }, + { 0, 0 } + }; + const struct cpu_default *def; +@@ -632,6 +657,8 @@ sparc_override_options (void) + /* TI ultrasparc III */ + /* ??? Check if %y issue still holds true in ultra3. */ + { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, ++ /* UltraSPARC T1 */ ++ { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, + { 0, 0, 0, 0 } + }; + const struct cpu_table *cpu; +@@ -741,7 +768,8 @@ sparc_override_options (void) + /* Supply a default value for align_functions. */ + if (align_functions == 0 + && (sparc_cpu == PROCESSOR_ULTRASPARC +- || sparc_cpu == PROCESSOR_ULTRASPARC3)) ++ || sparc_cpu == PROCESSOR_ULTRASPARC3 ++ || sparc_cpu == PROCESSOR_NIAGARA)) + align_functions = 32; + + /* Validate PCC_STRUCT_RETURN. */ +@@ -790,6 +818,9 @@ sparc_override_options (void) + case PROCESSOR_ULTRASPARC3: + sparc_costs = &ultrasparc3_costs; + break; ++ case PROCESSOR_NIAGARA: ++ sparc_costs = &niagara_costs; ++ break; + }; + + #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 +@@ -7099,7 +7130,8 @@ sparc_initialize_trampoline (rtx tramp, + aligned on a 16 byte boundary so one flush clears it all. */ + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); + if (sparc_cpu != PROCESSOR_ULTRASPARC +- && sparc_cpu != PROCESSOR_ULTRASPARC3) ++ && sparc_cpu != PROCESSOR_ULTRASPARC3 ++ && sparc_cpu != PROCESSOR_NIAGARA) + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, + plus_constant (tramp, 8))))); + +@@ -7141,7 +7173,8 @@ sparc64_initialize_trampoline (rtx tramp + emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); + + if (sparc_cpu != PROCESSOR_ULTRASPARC +- && sparc_cpu != PROCESSOR_ULTRASPARC3) ++ && sparc_cpu != PROCESSOR_ULTRASPARC3 ++ && sparc_cpu != PROCESSOR_NIAGARA) + emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); + + /* Call __enable_execute_stack after writing onto the stack to make sure +@@ -7321,6 +7354,8 @@ sparc_sched_init (FILE *dump ATTRIBUTE_U + static int + sparc_use_sched_lookahead (void) + { ++ if (sparc_cpu == PROCESSOR_NIAGARA) ++ return 0; + if (sparc_cpu == PROCESSOR_ULTRASPARC + || sparc_cpu == PROCESSOR_ULTRASPARC3) + return 4; +@@ -7336,6 +7371,7 @@ sparc_issue_rate (void) + { + switch (sparc_cpu) + { ++ case PROCESSOR_NIAGARA: + default: + return 1; + case PROCESSOR_V9: +--- gcc/config/sparc/sol2-bi.h (revision 111647) ++++ gcc/config/sparc/sol2-bi.h (revision 111648) +@@ -39,6 +39,15 @@ + #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" + #endif + ++#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara ++#undef CPP_CPU64_DEFAULT_SPEC ++#define CPP_CPU64_DEFAULT_SPEC "" ++#undef ASM_CPU32_DEFAULT_SPEC ++#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" ++#undef ASM_CPU64_DEFAULT_SPEC ++#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" ++#endif ++ + #if DEFAULT_ARCH32_P + #define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}" + #define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}" +@@ -57,7 +66,7 @@ + %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \ + %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ + %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ +-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ ++%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ + %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ + " + +@@ -66,7 +75,8 @@ + %{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \ + %{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \ + %{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ +-%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \ ++%{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ ++%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}} \ + %{!mcpu*:%(asm_cpu_default)} \ + " + +--- gcc/config/sparc/sparc.h (revision 111647) ++++ gcc/config/sparc/sparc.h (revision 111648) +@@ -206,7 +206,7 @@ extern enum cmodel sparc_cmodel; + which requires the following macro to be true if enabled. Prior to V9, + there are no instructions to even talk about memory synchronization. + Note that the UltraSPARC III processors don't implement RMO, unlike the +- UltraSPARC II processors. ++ UltraSPARC II processors. Niagara does not implement RMO either. + + Default to false; for example, Solaris never enables RMO, only ever uses + total memory ordering (TMO). */ +@@ -238,10 +238,12 @@ extern enum cmodel sparc_cmodel; + #define TARGET_CPU_sparc64 7 /* alias */ + #define TARGET_CPU_ultrasparc 8 + #define TARGET_CPU_ultrasparc3 9 ++#define TARGET_CPU_niagara 10 + + #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ +- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 ++ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ ++ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara + + #define CPP_CPU32_DEFAULT_SPEC "" + #define ASM_CPU32_DEFAULT_SPEC "" +@@ -262,6 +264,10 @@ extern enum cmodel sparc_cmodel; + #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" + #define ASM_CPU64_DEFAULT_SPEC "-Av9b" + #endif ++#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara ++#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" ++#define ASM_CPU64_DEFAULT_SPEC "-Av9b" ++#endif + + #else + +@@ -352,6 +358,7 @@ extern enum cmodel sparc_cmodel; + %{mcpu=v9:-D__sparc_v9__} \ + %{mcpu=ultrasparc:-D__sparc_v9__} \ + %{mcpu=ultrasparc3:-D__sparc_v9__} \ ++%{mcpu=niagara:-D__sparc_v9__} \ + %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ + " + #define CPP_ARCH32_SPEC "" +@@ -401,6 +408,7 @@ extern enum cmodel sparc_cmodel; + %{mcpu=v9:-Av9} \ + %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ + %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ ++%{mcpu=niagara:%{!mv8plus:-Av9b}} \ + %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ + " + +@@ -524,7 +532,8 @@ enum processor_type { + PROCESSOR_TSC701, + PROCESSOR_V9, + PROCESSOR_ULTRASPARC, +- PROCESSOR_ULTRASPARC3 ++ PROCESSOR_ULTRASPARC3, ++ PROCESSOR_NIAGARA + }; + + /* This is set from -m{cpu,tune}=xxx. */ +@@ -2137,7 +2146,8 @@ do { + || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ + || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ + ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ +- || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) ++ || sparc_cpu == PROCESSOR_ULTRASPARC3 \ ++ || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2) + + /* Provide the cost of a branch. For pre-v9 processors we use + a value of 3 to take into account the potential annulling of +@@ -2147,22 +2157,30 @@ do { + + On v9 and later, which have branch prediction facilities, we set + it to the depth of the pipeline as that is the cost of a +- mispredicted branch. */ ++ mispredicted branch. ++ ++ On Niagara, normal branches insert 3 bubbles into the pipe ++ and annulled branches insert 4 bubbles. */ + + #define BRANCH_COST \ + ((sparc_cpu == PROCESSOR_V9 \ + || sparc_cpu == PROCESSOR_ULTRASPARC) \ + ? 7 \ + : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ +- ? 9 : 3)) ++ ? 9 \ ++ : (sparc_cpu == PROCESSOR_NIAGARA \ ++ ? 4 \ ++ : 3))) + + #define PREFETCH_BLOCK \ + ((sparc_cpu == PROCESSOR_ULTRASPARC \ +- || sparc_cpu == PROCESSOR_ULTRASPARC3) \ ++ || sparc_cpu == PROCESSOR_ULTRASPARC3 \ ++ || sparc_cpu == PROCESSOR_NIAGARA) \ + ? 64 : 32) + + #define SIMULTANEOUS_PREFETCHES \ +- ((sparc_cpu == PROCESSOR_ULTRASPARC) \ ++ ((sparc_cpu == PROCESSOR_ULTRASPARC \ ++ || sparc_cpu == PROCESSOR_NIAGARA) \ + ? 2 \ + : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ + ? 8 : 3)) +--- gcc/config/sparc/linux64.h (revision 111647) ++++ gcc/config/sparc/linux64.h (revision 111648) +@@ -43,7 +43,8 @@ Boston, MA 02110-1301, USA. */ + + #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ +- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 ++ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ ++ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara + /* A 64 bit v9 compiler with stack-bias, + in a Medium/Low code model environment. */ + +--- gcc/config/sparc/sol2.h (revision 111647) ++++ gcc/config/sparc/sol2.h (revision 111648) +@@ -41,11 +41,17 @@ Boston, MA 02110-1301, USA. */ + #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb" + #endif + ++#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara ++#undef ASM_CPU_DEFAULT_SPEC ++#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb" ++#endif ++ + #undef ASM_CPU_SPEC + #define ASM_CPU_SPEC "\ + %{mcpu=v9:-xarch=v8plus} \ + %{mcpu=ultrasparc:-xarch=v8plusa} \ + %{mcpu=ultrasparc3:-xarch=v8plusb} \ ++%{mcpu=niagara:-xarch=v8plusb} \ + %{!mcpu*:%(asm_cpu_default)} \ + " + diff --git a/gcc41.spec b/gcc41.spec index ca6700f..0a78ce0 100644 --- a/gcc41.spec +++ b/gcc41.spec @@ -1,6 +1,6 @@ -%define DATE 20070723 +%define DATE 20070816 %define gcc_version 4.1.2 -%define gcc_release 17 +%define gcc_release 18 %define _unpackaged_files_terminate_build 0 %define multilib_64_archs sparc64 ppc64 s390x x86_64 %define include_gappletviewer 1 @@ -26,7 +26,10 @@ Summary: Various compilers (C, C++, Objective-C, Java, ...) Name: gcc Version: %{gcc_version} Release: %{gcc_release} -License: GPL +# libgcc, libgfortran, libmudflap and crtstuff have an exception which allows +# linking it into any kind of programs or shared libraries without +# restrictions. +License: GPLv2+ and GPLv2+ with exceptions Group: Development/Languages Source0: gcc-%{version}-%{DATE}.tar.bz2 Source1: libgcc_post_upgrade.c @@ -135,6 +138,10 @@ Patch21: gcc41-rh235008.patch Patch22: gcc41-build-id.patch Patch23: gcc41-pr28690.patch Patch24: gcc41-rh247256.patch +Patch25: gcc41-pr22244.patch +Patch26: gcc41-pr32678.patch +Patch27: gcc41-pr32992.patch +Patch28: gcc41-sparc-niagara.patch # On ARM EABI systems, we do want -gnueabi to be part of the # target triple. @@ -241,7 +248,7 @@ Summary: Fortran 95 support Group: Development/Languages Requires: gcc = %{version}-%{release} Requires: libgfortran = %{version}-%{release} -BuildRequires: gmp-devel >= 4.1.2-8 +BuildRequires: gmp-devel >= 4.1.2-8, mpfr-devel >= 2.2.1 Prereq: /sbin/install-info Obsoletes: gcc3-g77 Obsoletes: gcc-g77 @@ -442,6 +449,10 @@ which are required to run programs compiled with the GNAT. %patch22 -p0 -b .build-id~ %patch23 -p0 -b .pr28690~ %patch24 -p0 -b .rh247256~ +%patch25 -p0 -b .pr22244~ +%patch26 -p0 -b .pr32678~ +%patch27 -p0 -b .pr32992~ +%patch28 -p0 -b .sparc-niagara~ sed -i -e 's/4\.1\.3/4.1.2/' gcc/BASE-VER gcc/version.c sed -i -e 's/" (Red Hat[^)]*)"/" (Red Hat %{version}-%{gcc_release})"/' gcc/version.c @@ -1565,6 +1576,19 @@ fi %doc rpm.doc/changelogs/libmudflap/ChangeLog* %changelog +* Thu Aug 16 2007 Jakub Jelinek 4.1.2-18 +- update from gcc-4_1-branch (-r126830:127528) + - PR c++/17763 +- fix --build-id patch on ia64 (#251936) +- fix fortran Tx format handling (Jerry DeLisle, #252152, + PR libgfortran/32678) +- add support for Sun UltraSPARC T1 chips - -mcpu=niagara (David S. Miller) +- don't NRV optimize fields inside anonymous unions (PR c++/32992) +- fortran debuginfo improvements for constant bound arrays (#248541, + PR fortran/22244) +- BuildRequire mpfr-devel +- update License tag + * Tue Jul 24 2007 Jakub Jelinek 4.1.2-17 - fix {,Build}Requires from last change (#249384) diff --git a/sources b/sources index 67157cc..216d6cb 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -1fbcf4ea119fcc5c93a5229b20af30fc gcc-4.1.2-20070723.tar.bz2 +599a243fcc5e34eac99032611e91618b gcc-4.1.2-20070816.tar.bz2