Remove obsolete patches
These patches are already included. Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
parent
1d5f1f1838
commit
121a76ad9b
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@ -1,220 +0,0 @@
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From 6aafb75646ccb308bf316e0b3a7873b809d1a64a Mon Sep 17 00:00:00 2001
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From: kito <kito@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Thu, 19 Sep 2019 06:38:23 +0000
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Subject: [PATCH] RISC-V: Fix bad insn splits with paradoxical subregs.
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Shifting by more than the size of a SUBREG_REG doesn't work, so we either
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need to disable splits if an input is paradoxical, or else we need to
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generate a clean temporary for intermediate results.
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Jakub wrote the first version of this patch, so gets primary credit for it.
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gcc/
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PR target/91635
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* config/riscv/riscv.md (zero_extendsidi2, zero_extendhi<GPR:mode>2,
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extend<SHORT:mode><SUPERQI:mode>2): Don't split if
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paradoxical_subreg_p (operands[0]).
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(*lshrsi3_zero_extend_3+1, *lshrsi3_zero_extend_3+2): Add clobber and
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use as intermediate value.
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gcc/testsuite/
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PR target/91635
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* gcc.c-torture/execute/pr91635.c: New test.
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* gcc.target/riscv/shift-shift-4.c: New test.
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* gcc.target/riscv/shift-shift-5.c: New test.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275929 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/ChangeLog | 13 +++++
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gcc/config/riscv/riscv.md | 30 +++++++---
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gcc/testsuite/ChangeLog | 11 ++++
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gcc/testsuite/gcc.c-torture/execute/pr91635.c | 57 +++++++++++++++++++
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.../gcc.target/riscv/shift-shift-4.c | 13 +++++
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.../gcc.target/riscv/shift-shift-5.c | 16 ++++++
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6 files changed, 131 insertions(+), 9 deletions(-)
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create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr91635.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-4.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-5.c
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diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
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index a8bac170e72f..7850c41f3c7e 100644
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--- a/gcc/config/riscv/riscv.md
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+++ b/gcc/config/riscv/riscv.md
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@@ -1051,7 +1051,9 @@
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"@
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#
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lwu\t%0,%1"
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- "&& reload_completed && REG_P (operands[1])"
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+ "&& reload_completed
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+ && REG_P (operands[1])
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+ && !paradoxical_subreg_p (operands[0])"
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[(set (match_dup 0)
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(ashift:DI (match_dup 1) (const_int 32)))
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(set (match_dup 0)
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@@ -1068,7 +1070,9 @@
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"@
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#
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lhu\t%0,%1"
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- "&& reload_completed && REG_P (operands[1])"
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+ "&& reload_completed
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+ && REG_P (operands[1])
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+ && !paradoxical_subreg_p (operands[0])"
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[(set (match_dup 0)
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(ashift:GPR (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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@@ -1117,7 +1121,9 @@
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"@
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#
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l<SHORT:size>\t%0,%1"
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- "&& reload_completed && REG_P (operands[1])"
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+ "&& reload_completed
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+ && REG_P (operands[1])
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+ && !paradoxical_subreg_p (operands[0])"
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[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
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{
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@@ -1765,15 +1771,20 @@
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;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into
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;; two logical shifts. Otherwise it requires 3 instructions: lui,
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;; xor/addi/srli, and.
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+
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+;; Generating a temporary for the shift output gives better combiner results;
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+;; and also fixes a problem where op0 could be a paradoxical reg and shifting
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+;; by amounts larger than the size of the SUBREG_REG doesn't work.
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(define_split
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[(set (match_operand:GPR 0 "register_operand")
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(and:GPR (match_operand:GPR 1 "register_operand")
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- (match_operand:GPR 2 "p2m1_shift_operand")))]
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+ (match_operand:GPR 2 "p2m1_shift_operand")))
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+ (clobber (match_operand:GPR 3 "register_operand"))]
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""
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- [(set (match_dup 0)
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+ [(set (match_dup 3)
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(ashift:GPR (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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- (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
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+ (lshiftrt:GPR (match_dup 3) (match_dup 2)))]
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{
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/* Op2 is a VOIDmode constant, so get the mode size from op1. */
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operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1]))
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@@ -1785,12 +1796,13 @@
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI (match_operand:DI 1 "register_operand")
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- (match_operand:DI 2 "high_mask_shift_operand")))]
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+ (match_operand:DI 2 "high_mask_shift_operand")))
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+ (clobber (match_operand:DI 3 "register_operand"))]
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"TARGET_64BIT"
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- [(set (match_dup 0)
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+ [(set (match_dup 3)
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(lshiftrt:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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- (ashift:DI (match_dup 0) (match_dup 2)))]
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+ (ashift:DI (match_dup 3) (match_dup 2)))]
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{
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operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2])));
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})
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diff --git a/gcc/testsuite/gcc.c-torture/execute/pr91635.c b/gcc/testsuite/gcc.c-torture/execute/pr91635.c
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new file mode 100644
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index 000000000000..878a491fc360
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--- /dev/null
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+++ b/gcc/testsuite/gcc.c-torture/execute/pr91635.c
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@@ -0,0 +1,57 @@
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+/* PR target/91635 */
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+
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+#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \
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+ && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8
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+unsigned short b, c;
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+int u, v, w, x;
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+
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+__attribute__ ((noipa)) int
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+foo (unsigned short c)
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+{
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+ c <<= __builtin_add_overflow (-c, -1, &b);
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+ c >>= 1;
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+ return c;
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+}
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+
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+__attribute__ ((noipa)) int
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+bar (unsigned short b)
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+{
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+ b <<= -14 & 15;
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+ b = b >> -~1;
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+ return b;
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+}
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+
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+__attribute__ ((noipa)) int
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+baz (unsigned short e)
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+{
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+ e <<= 1;
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+ e >>= __builtin_add_overflow (8719476735, u, &v);
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+ return e;
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+}
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+
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+__attribute__ ((noipa)) int
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+qux (unsigned int e)
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+{
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+ c = ~1;
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+ c *= e;
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+ c = c >> (-15 & 5);
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+ return c + w + x;
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+}
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+#endif
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+
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+int
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+main ()
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+{
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+#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \
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+ && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8
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+ if (foo (0xffff) != 0x7fff)
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+ __builtin_abort ();
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+ if (bar (5) != 5)
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+ __builtin_abort ();
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+ if (baz (~0) != 0x7fff)
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+ __builtin_abort ();
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+ if (qux (2) != 0x7ffe)
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+ __builtin_abort ();
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+#endif
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+ return 0;
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+}
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diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
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new file mode 100644
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index 000000000000..72a45ee87ae6
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
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@@ -0,0 +1,13 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */
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+
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+/* One zero-extend shift can be eliminated by modifying the constant in the
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+ greater than test. Started working after modifying the splitter
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+ lshrsi3_zero_extend_3+1 to use a temporary reg for the first split dest. */
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+int
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+sub (int i)
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+{
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+ i &= 0x7fffffff;
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+ return i > 0x7f800000;
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+}
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+/* { dg-final { scan-assembler-not "srli" } } */
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diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
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new file mode 100644
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index 000000000000..5b2ae89a471d
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
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@@ -0,0 +1,16 @@
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+/* { dg-do compile } */
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+/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
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+
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+/* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST
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+ note. */
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+unsigned long
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+sub (long l)
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+{
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+ union u {
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+ struct s { int a : 19; unsigned int b : 13; int x; } s;
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+ long l;
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+ } u;
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+ u.l = l;
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+ return u.s.b;
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+}
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+/* { dg-final { scan-assembler "srliw" } } */
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@ -1,227 +0,0 @@
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From d6279ef7800d8d3c0cec208900e9c443af875bd1 Mon Sep 17 00:00:00 2001
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From: kito <kito@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Fri, 20 Sep 2019 10:41:51 +0000
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Subject: [PATCH] RISC-V: Fix more splitters accidentally calling gen_reg_rtx.
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PR target/91683
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* config/riscv/riscv-protos.h (riscv_split_symbol): New bool parameter.
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(riscv_move_integer): Likewise.
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* config/riscv/riscv.c (riscv_split_integer): Pass FALSE for new
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riscv_move_integer arg.
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(riscv_legitimize_move): Likewise.
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(riscv_force_temporary): New parameter in_splitter. Don't call
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force_reg if true.
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(riscv_unspec_offset_high): Pass FALSE for new riscv_force_temporary
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arg.
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(riscv_add_offset): Likewise.
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(riscv_split_symbol): New parameter in_splitter. Pass to
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riscv_force_temporary.
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(riscv_legitimize_address): Pass FALSE for new riscv_split_symbol
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arg.
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(riscv_move_integer): New parameter in_splitter. New local
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can_create_psuedo. Don't call riscv_split_integer or force_reg when
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in_splitter TRUE.
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(riscv_legitimize_const_move): Pass FALSE for new riscv_move_integer,
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riscv_split_symbol, and riscv_force_temporary args.
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* config/riscv/riscv.md (low<mode>+1): Pass TRUE for new
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riscv_move_integer arg.
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(low<mode>+2): Pass TRUE for new riscv_split_symbol arg.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275997 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/config/riscv/riscv-protos.h | 4 +--
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gcc/config/riscv/riscv.c | 45 ++++++++++++++++++++-------------
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gcc/config/riscv/riscv.md | 6 ++---
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4 files changed, 62 insertions(+), 22 deletions(-)
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diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
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index 8b510f87df87..5b0bbdd7cb4e 100644
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--- a/gcc/config/riscv/riscv-protos.h
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+++ b/gcc/config/riscv/riscv-protos.h
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@@ -44,10 +44,10 @@ extern int riscv_const_insns (rtx);
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extern int riscv_split_const_insns (rtx);
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extern int riscv_load_store_insns (rtx, rtx_insn *);
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extern rtx riscv_emit_move (rtx, rtx);
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-extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
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+extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool);
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extern bool riscv_split_symbol_type (enum riscv_symbol_type);
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extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
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-extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
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+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, bool);
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extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
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extern rtx riscv_subword (rtx, bool);
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extern bool riscv_split_64bit_move_p (rtx, rtx);
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diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
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index 35219956c80d..5cb295d3abba 100644
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--- a/gcc/config/riscv/riscv.c
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+++ b/gcc/config/riscv/riscv.c
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@@ -508,8 +508,8 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)
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unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
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rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode);
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- riscv_move_integer (hi, hi, hival);
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- riscv_move_integer (lo, lo, loval);
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+ riscv_move_integer (hi, hi, hival, FALSE);
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+ riscv_move_integer (lo, lo, loval, FALSE);
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hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32));
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hi = force_reg (mode, hi);
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@@ -1021,9 +1021,12 @@ riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y)
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are allowed, copy it into a new register, otherwise use DEST. */
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static rtx
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-riscv_force_temporary (rtx dest, rtx value)
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+riscv_force_temporary (rtx dest, rtx value, bool in_splitter)
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{
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- if (can_create_pseudo_p ())
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+ /* We can't call gen_reg_rtx from a splitter, because this might realloc
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+ the regno_reg_rtx array, which would invalidate reg rtx pointers in the
|
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+ combine undo buffer. */
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+ if (can_create_pseudo_p () && !in_splitter)
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return force_reg (Pmode, value);
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else
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{
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@@ -1082,7 +1085,7 @@ static rtx
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riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type)
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{
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addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type));
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- return riscv_force_temporary (temp, addr);
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+ return riscv_force_temporary (temp, addr, FALSE);
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}
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/* Load an entry from the GOT for a TLS GD access. */
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@@ -1130,7 +1133,8 @@ static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym)
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is guaranteed to be a legitimate address for mode MODE. */
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bool
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-riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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+riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out,
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+ bool in_splitter)
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{
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enum riscv_symbol_type symbol_type;
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@@ -1146,7 +1150,7 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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case SYMBOL_ABSOLUTE:
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{
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
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- high = riscv_force_temporary (temp, high);
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+ high = riscv_force_temporary (temp, high, in_splitter);
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*low_out = gen_rtx_LO_SUM (Pmode, high, addr);
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}
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break;
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@@ -1205,8 +1209,9 @@ riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
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overflow, so we need to force a sign-extension check. */
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high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
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offset = CONST_LOW_PART (offset);
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- high = riscv_force_temporary (temp, high);
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- reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
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+ high = riscv_force_temporary (temp, high, FALSE);
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+ reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg),
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+ FALSE);
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}
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return plus_constant (Pmode, reg, offset);
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}
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@@ -1315,7 +1320,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
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return riscv_legitimize_tls_address (x);
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/* See if the address can split into a high part and a LO_SUM. */
|
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- if (riscv_split_symbol (NULL, x, mode, &addr))
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+ if (riscv_split_symbol (NULL, x, mode, &addr, FALSE))
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return riscv_force_address (addr, mode);
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/* Handle BASE + OFFSET using riscv_add_offset. */
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@@ -1337,17 +1342,23 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
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/* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */
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void
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-riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
|
||||
+riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
|
||||
+ bool in_splitter)
|
||||
{
|
||||
struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
|
||||
machine_mode mode;
|
||||
int i, num_ops;
|
||||
rtx x;
|
||||
|
||||
+ /* We can't call gen_reg_rtx from a splitter, because this might realloc
|
||||
+ the regno_reg_rtx array, which would invalidate reg rtx pointers in the
|
||||
+ combine undo buffer. */
|
||||
+ bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter;
|
||||
+
|
||||
mode = GET_MODE (dest);
|
||||
num_ops = riscv_build_integer (codes, value, mode);
|
||||
|
||||
- if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */
|
||||
+ if (can_create_pseudo && num_ops > 2 /* not a simple constant */
|
||||
&& num_ops >= riscv_split_integer_cost (value))
|
||||
x = riscv_split_integer (value, mode);
|
||||
else
|
||||
@@ -1357,7 +1368,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
|
||||
|
||||
for (i = 1; i < num_ops; i++)
|
||||
{
|
||||
- if (!can_create_pseudo_p ())
|
||||
+ if (!can_create_pseudo)
|
||||
x = riscv_emit_set (temp, x);
|
||||
else
|
||||
x = force_reg (mode, x);
|
||||
@@ -1381,12 +1392,12 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
|
||||
/* Split moves of big integers into smaller pieces. */
|
||||
if (splittable_const_int_operand (src, mode))
|
||||
{
|
||||
- riscv_move_integer (dest, dest, INTVAL (src));
|
||||
+ riscv_move_integer (dest, dest, INTVAL (src), FALSE);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Split moves of symbolic constants into high/low pairs. */
|
||||
- if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
|
||||
+ if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE))
|
||||
{
|
||||
riscv_emit_set (dest, src);
|
||||
return;
|
||||
@@ -1407,7 +1418,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
|
||||
if (offset != const0_rtx
|
||||
&& (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ()))
|
||||
{
|
||||
- base = riscv_force_temporary (dest, base);
|
||||
+ base = riscv_force_temporary (dest, base, FALSE);
|
||||
riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset)));
|
||||
return;
|
||||
}
|
||||
@@ -1416,7 +1427,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
|
||||
|
||||
/* When using explicit relocs, constant pool references are sometimes
|
||||
not legitimate addresses. */
|
||||
- riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
|
||||
+ riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE);
|
||||
riscv_emit_move (dest, src);
|
||||
}
|
||||
|
||||
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
|
||||
index 7850c41f3c7e..e40535c9e405 100644
|
||||
--- a/gcc/config/riscv/riscv.md
|
||||
+++ b/gcc/config/riscv/riscv.md
|
||||
@@ -1284,7 +1284,7 @@
|
||||
""
|
||||
[(const_int 0)]
|
||||
{
|
||||
- riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]));
|
||||
+ riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), TRUE);
|
||||
DONE;
|
||||
})
|
||||
|
||||
@@ -1293,11 +1293,11 @@
|
||||
[(set (match_operand:P 0 "register_operand")
|
||||
(match_operand:P 1))
|
||||
(clobber (match_operand:P 2 "register_operand"))]
|
||||
- "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
|
||||
+ "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)"
|
||||
[(set (match_dup 0) (match_dup 3))]
|
||||
{
|
||||
riscv_split_symbol (operands[2], operands[1],
|
||||
- MAX_MACHINE_MODE, &operands[3]);
|
||||
+ MAX_MACHINE_MODE, &operands[3], TRUE);
|
||||
})
|
||||
|
||||
;; 64-bit integer moves
|
11
gcc.spec
11
gcc.spec
|
@ -255,12 +255,6 @@ Patch9: gcc9-Wno-format-security.patch
|
|||
Patch10: gcc9-rh1574936.patch
|
||||
Patch11: gcc9-d-shared-libphobos.patch
|
||||
|
||||
# RISC-V Backports (official, but not yet in Fedora)
|
||||
# Patches taken from:
|
||||
# https://github.com/gcc-mirror/gcc/commits/gcc-9-branch
|
||||
Patch100: 6aafb75646ccb308bf316e0b3a7873b809d1a64a.patch
|
||||
Patch101: d6279ef7800d8d3c0cec208900e9c443af875bd1.patch
|
||||
|
||||
Patch1000: nvptx-tools-no-ptxas.patch
|
||||
Patch1001: nvptx-tools-build.patch
|
||||
Patch1002: nvptx-tools-glibc.patch
|
||||
|
@ -777,11 +771,6 @@ to NVidia PTX capable devices if available.
|
|||
%endif
|
||||
%patch11 -p0 -b .d-shared-libphobos~
|
||||
|
||||
%ifarch riscv64
|
||||
%patch100 -p1 -b .riscv64_1~
|
||||
%patch101 -p1 -b .riscv64_2~
|
||||
%endif
|
||||
|
||||
cd nvptx-tools-%{nvptx_tools_gitrev}
|
||||
%patch1000 -p1 -b .nvptx-tools-no-ptxas~
|
||||
%patch1001 -p1 -b .nvptx-tools-build~
|
||||
|
|
Loading…
Reference in New Issue