diff --git a/0001-Enable-RISC-V-in-libphobos-especially-math.d.patch b/0001-Enable-RISC-V-in-libphobos-especially-math.d.patch
index 851ca81..37be084 100644
--- a/0001-Enable-RISC-V-in-libphobos-especially-math.d.patch
+++ b/0001-Enable-RISC-V-in-libphobos-especially-math.d.patch
@@ -1,13 +1,13 @@
-From a0308671e12ccbd235717aacce15d06f37aa758a Mon Sep 17 00:00:00 2001
+From 35ced3822a12415f7bf7307f43c503736aa4b8e8 Mon Sep 17 00:00:00 2001
 From: David Abdurachmanov <david.abdurachmanov@gmail.com>
-Date: Wed, 23 Jan 2019 10:55:00 +0100
-Subject: [PATCH] Enable RISC-V in libphobos (especially math.d)
+Date: Wed, 23 Jan 2019 21:45:01 +0100
+Subject: [PATCH] Add RISCV support in libphobos
 
 Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
 ---
  .../allocator/building_blocks/region.d        |  3 +-
- libphobos/src/std/math.d                      | 59 +++++++++++++++++++
- 2 files changed, 61 insertions(+), 1 deletion(-)
+ libphobos/src/std/math.d                      | 61 +++++++++++++++++++
+ 2 files changed, 63 insertions(+), 1 deletion(-)
 
 diff --git a/libphobos/src/std/experimental/allocator/building_blocks/region.d b/libphobos/src/std/experimental/allocator/building_blocks/region.d
 index 80157aee7e6..ad90d17df00 100644
@@ -24,10 +24,19 @@ index 80157aee7e6..ad90d17df00 100644
      else version (SystemZ) enum growDownwards = Yes.growDownwards;
      else static assert(0, "Dunno how the stack grows on this architecture.");
 diff --git a/libphobos/src/std/math.d b/libphobos/src/std/math.d
-index 7bb4d7c23db..42493364596 100644
+index 7bb4d7c23db..ba9b03c4da9 100644
 --- a/libphobos/src/std/math.d
 +++ b/libphobos/src/std/math.d
-@@ -4654,6 +4654,7 @@ private:
+@@ -160,6 +160,8 @@ version (MIPS32)    version = MIPS_Any;
+ version (MIPS64)    version = MIPS_Any;
+ version (AArch64)   version = ARM_Any;
+ version (ARM)       version = ARM_Any;
++version (RISCV32)   version = RISCV_Any;
++version (RISCV64)   version = RISCV_Any;
+ 
+ version (D_InlineAsm_X86)
+ {
+@@ -4654,6 +4656,7 @@ private:
      // The Pentium SSE2 status register is 32 bits.
      // The ARM and PowerPC FPSCR is a 32-bit register.
      // The SPARC FSR is a 32bit register (64 bits for SPARC 7 & 8, but high bits are uninteresting).
@@ -35,7 +44,7 @@ index 7bb4d7c23db..42493364596 100644
      uint flags;
  
      version (CRuntime_Microsoft)
-@@ -4725,6 +4726,15 @@ private:
+@@ -4725,6 +4728,15 @@ private:
                      return result;
                  }
              }
@@ -51,7 +60,7 @@ index 7bb4d7c23db..42493364596 100644
              else
                  assert(0, "Not yet supported");
          }
-@@ -4799,6 +4809,15 @@ private:
+@@ -4799,6 +4811,15 @@ private:
                      }
                  }
              }
@@ -67,7 +76,7 @@ index 7bb4d7c23db..42493364596 100644
              else
                  assert(0, "Not yet supported");
          }
-@@ -4968,6 +4987,10 @@ else version (PPC_Any)
+@@ -4968,6 +4989,10 @@ else version (PPC_Any)
  {
      version = IeeeFlagsSupport;
  }
@@ -78,7 +87,7 @@ index 7bb4d7c23db..42493364596 100644
  else version (MIPS_Any)
  {
      version = IeeeFlagsSupport;
-@@ -5162,6 +5185,21 @@ struct FloatingPointControl
+@@ -5162,6 +5187,21 @@ struct FloatingPointControl
                                   | inexactException,
          }
      }
@@ -100,7 +109,7 @@ index 7bb4d7c23db..42493364596 100644
      else version (SPARC64)
      {
          enum : ExceptionMask
-@@ -5292,6 +5330,10 @@ private:
+@@ -5292,6 +5332,10 @@ private:
      {
          alias ControlState = uint;
      }
@@ -111,7 +120,7 @@ index 7bb4d7c23db..42493364596 100644
      else version (SPARC64)
      {
          alias ControlState = ulong;
-@@ -5359,6 +5401,15 @@ private:
+@@ -5359,6 +5403,15 @@ private:
                  }
                  return cont;
              }
@@ -127,7 +136,7 @@ index 7bb4d7c23db..42493364596 100644
              else
                  assert(0, "Not yet supported");
          }
-@@ -5444,6 +5495,14 @@ private:
+@@ -5444,6 +5497,14 @@ private:
                      }
                  }
              }