diff --git a/6e7e5943619a2c20d93fc7089c885483786558bc.patch b/6e7e5943619a2c20d93fc7089c885483786558bc.patch new file mode 100644 index 0000000..ad6e04a --- /dev/null +++ b/6e7e5943619a2c20d93fc7089c885483786558bc.patch @@ -0,0 +1,90 @@ +From 6e7e5943619a2c20d93fc7089c885483786558bc Mon Sep 17 00:00:00 2001 +From: Pan Li +Date: Fri, 12 Apr 2024 16:38:18 +0800 +Subject: [PATCH] RISC-V: Fix Werror=sign-compare in riscv_validate_vector_type +MIME-Version: 1.0 +Content-Type: text/plain; charset=utf8 +Content-Transfer-Encoding: 8bit + +This patch would like to fix the Werror=sign-compare similar to below: + +gcc/config/riscv/riscv.cc: In function ‘void +riscv_validate_vector_type(const_tree, const char*)’: +gcc/config/riscv/riscv.cc:5614:23: error: comparison of integer +expressions of different signedness: ‘int’ and ‘unsigned int’ +[-Werror=sign-compare] + 5614 | if (TARGET_MIN_VLEN < required_min_vlen) + +The TARGET_MIN_VLEN is *int* by default but the required_min_vlen +returned from riscv_vector_required_min_vlen is **unsigned**. Thus, +adjust the related function and reference variable(s) to int type +to avoid such kind of Werror. + +The below test suite is passed for this patch. +* The rv64gcv fully regression tests. + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_vector_float_type_p): Take int + as the return value instead of unsigned. + (riscv_vector_element_bitsize): Ditto. + (riscv_vector_required_min_vlen): Ditto. + (riscv_validate_vector_type): Take int type for local variable(s). + +Signed-off-by: Pan Li +--- + gcc/config/riscv/riscv.cc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index e5f00806bb9..74445bc977c 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -5499,7 +5499,7 @@ riscv_vector_float_type_p (const_tree type) + return strstr (name, "vfloat") != NULL; + } + +-static unsigned ++static int + riscv_vector_element_bitsize (const_tree type) + { + machine_mode mode = TYPE_MODE (type); +@@ -5523,7 +5523,7 @@ riscv_vector_element_bitsize (const_tree type) + gcc_unreachable (); + } + +-static unsigned ++static int + riscv_vector_required_min_vlen (const_tree type) + { + machine_mode mode = TYPE_MODE (type); +@@ -5531,7 +5531,7 @@ riscv_vector_required_min_vlen (const_tree type) + if (riscv_v_ext_mode_p (mode)) + return TARGET_MIN_VLEN; + +- unsigned element_bitsize = riscv_vector_element_bitsize (type); ++ int element_bitsize = riscv_vector_element_bitsize (type); + const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); + + if (strstr (name, "bool64") != NULL) +@@ -5569,7 +5569,7 @@ riscv_validate_vector_type (const_tree type, const char *hint) + return; + } + +- unsigned element_bitsize = riscv_vector_element_bitsize (type); ++ int element_bitsize = riscv_vector_element_bitsize (type); + bool int_type_p = riscv_vector_int_type_p (type); + + if (int_type_p && element_bitsize == 64 +@@ -5609,7 +5609,7 @@ riscv_validate_vector_type (const_tree type, const char *hint) + return; + } + +- unsigned required_min_vlen = riscv_vector_required_min_vlen (type); ++ int required_min_vlen = riscv_vector_required_min_vlen (type); + + if (TARGET_MIN_VLEN < required_min_vlen) + { +-- +2.39.3 + diff --git a/dc51a6428f6d8e5a57b8b1bf559145288e87660b.patch b/dc51a6428f6d8e5a57b8b1bf559145288e87660b.patch new file mode 100644 index 0000000..489cb22 --- /dev/null +++ b/dc51a6428f6d8e5a57b8b1bf559145288e87660b.patch @@ -0,0 +1,128 @@ +From dc51a6428f6d8e5a57b8b1bf559145288e87660b Mon Sep 17 00:00:00 2001 +From: Pan Li +Date: Fri, 12 Apr 2024 11:12:24 +0800 +Subject: [PATCH] RISC-V: Bugfix ICE non-vector in + TARGET_FUNCTION_VALUE_REGNO_P + +This patch would like to fix one ICE when vector is not enabled +in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector +regno is available if and only if the TARGET_VECTOR is true. The +previous implement missed this condition and then result in ICE +when rv64gc build option without vector. + +The below test suite is passed for this patch. + +* The rv64gcv fully regression tests. +* The rv64gc fully regression tests. + + PR target/114639 + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_function_value_regno_p): Add + TARGET_VECTOR predicate for V_RETURN regno. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/pr114639-1.c: New test. + * gcc.target/riscv/pr114639-2.c: New test. + * gcc.target/riscv/pr114639-3.c: New test. + * gcc.target/riscv/pr114639-4.c: New test. + +Signed-off-by: Pan Li +--- + gcc/config/riscv/riscv.cc | 2 +- + gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ + gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ + gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ + gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ + 5 files changed, 45 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 91f017dd52a..e5f00806bb9 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) + if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) + return true; + +- if (regno == V_RETURN) ++ if (TARGET_VECTOR && regno == V_RETURN) + return true; + + return false; +diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c +new file mode 100644 +index 00000000000..f41723193a4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c +@@ -0,0 +1,11 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ ++ ++g (a, b) {} ++ ++f (xx) ++ void* xx; ++{ ++ __builtin_apply ((void*)g, xx, 200); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c +new file mode 100644 +index 00000000000..0c402c4b254 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c +@@ -0,0 +1,11 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ ++ ++g (a, b) {} ++ ++f (xx) ++ void* xx; ++{ ++ __builtin_apply ((void*)g, xx, 200); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c +new file mode 100644 +index 00000000000..ffb0d6d162d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c +@@ -0,0 +1,11 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ ++ ++g (a, b) {} ++ ++f (xx) ++ void* xx; ++{ ++ __builtin_apply ((void*)g, xx, 200); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c +new file mode 100644 +index 00000000000..a6e229101ef +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c +@@ -0,0 +1,11 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ ++ ++g (a, b) {} ++ ++f (xx) ++ void* xx; ++{ ++ __builtin_apply ((void*)g, xx, 200); ++} +-- +2.39.3 + diff --git a/gcc.spec b/gcc.spec index 9d2d8e5..927dddd 100644 --- a/gcc.spec +++ b/gcc.spec @@ -41,7 +41,7 @@ %else %global build_ada 0 %endif -%global build_objc 0 +%global build_objc 1 %ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64 %global build_go 1 %else @@ -141,7 +141,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: gcc Version: %{gcc_version} -Release: %{gcc_release}.15.0.riscv64%{?dist} +Release: %{gcc_release}.15.1.riscv64%{?dist} # License notes for some of the less obvious ones: # gcc/doc/cppinternals.texi: Linux-man-pages-copyleft-2-para # isl: MIT, BSD-2-Clause @@ -309,6 +309,9 @@ Patch9: gcc14-Wno-format-security.patch Patch10: gcc14-rh1574936.patch Patch11: gcc14-d-shared-libphobos.patch +Patch15: dc51a6428f6d8e5a57b8b1bf559145288e87660b.patch +Patch16: 6e7e5943619a2c20d93fc7089c885483786558bc.patch + Patch50: isl-rh2155127.patch Patch100: gcc14-fortran-fdec-duplicates.patch @@ -907,6 +910,9 @@ so that there cannot be any synchronization problems. %endif %patch -P11 -p0 -b .d-shared-libphobos~ +%patch -P15 -p0 -b .non-vec-ice +%patch -P16 -p0 -b .vec-sign-compare + %patch -P50 -p0 -b .rh2155127~ touch -r isl-0.24/m4/ax_prog_cxx_for_build.m4 isl-0.24/m4/ax_prog_cc_for_build.m4 @@ -3621,6 +3627,9 @@ end %endif %changelog +* Wed Apr 17 2024 David Abdurachamnov 14.0.1-0.15.1.riscv64 +- Backport PRs a couple commits + * Tue Apr 16 2024 David Abdurachamnov 14.0.1-0.15.0.riscv64 - Disable LTO bootstrap (experiment)